i-manager Publications

i-manager's Journal on Electronics Engineering (JELE)

Current Issue Vol. 15 Issue 1

Most Cited

Volume 7 Issue 4 June - August 2017

Research Paper

Analysis and Design of Body Driven Dynamic Latch based Comparator in Low Supply Voltages with nMOS Driver

Vijay Savani* , N. M. Devashrayee**

* Assistant Professor, Department of Electronics and Communication Engineering, Institute of Technology, Nirma University, Gujarat, India.

** Professor, Department of Electronics and Communication Engineering, Institute of Technology, Nirma University, Gujarat, India.

Savani, V., and Devashrayee, N. M. (2017). Analysis and Design of Body Driven Dynamic Latch based Comparator in Low Supply Voltages with nMOS Driver. i-manager’s Journal on Electronics Engineering, 7(4), 1-8. https://doi.org/10.26634/jele.7.4.13683

Abstract

High speed operation, ultra-low power utilization, and efficiency are the need of battery operated handheld devices. This need forces the use of dynamic latch based comparator, having characteristics of using low supply voltage, high speed, and less power utilization. In this paper, the delay analysis of the body driven p-channel metal oxide semiconductor with a low voltage dynamic comparator is presented. The enhancement in the present structure as suggested by the previous work for fast operation in lower supply voltage is presented. Finally, the modification of the structure is proposed with the help of n-channel metal oxide semiconductor driver based design. Simulation results in 90 nm complementary metal oxide semiconductor technology are carried out for previous work and proposed design. The maximum clock frequency of the modified comparator topology can be achieved up to 500 MHz at a supply voltage of 1 V while consuming 67% less power compared to the previously reported topology.

References

[1]. Akbari, M., Maymandi-Nejad, M., & Mirbozorgi, S. A. (2013, May). A new rail-to-rail ultra low voltage high speed st comparator. In Electrical Engineering (ICEE), 2013 21 Iranian Conference on (pp. 1-6). IEEE.

[2]. Allen, P. E., & Holberg, D. R. (2002). CMOS Analog Circuit Design. Oxford Univ. Press.

[3]. Ay, S. U. (2011). A sub-1áVolt 10-bit supply boosted SAR ADC design in standard CMOS. Analog Integrated Circuits and Signal Processing, 66(2), 213-221.

[4]. Babayan-Mashhadi, S., & Lotfi, R. (2014). Analysis and design of a low-voltage low-power double-tail comparator. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22(2), 343-352.

[5]. Babayan-Mashhadi, S., & Sarvaghad-Moghaddam, M. (2014, May). Analysis and Design of Dynamic Comparators in ultra-low supply voltages. In Electrical nd Engineering (ICEE), 2014 22 Iranian Conference on (pp. 255-258). IEEE.

[6]. Bhatasana, P. M., Savani, V. G., & Mecwan, A. I. (2013). Implementation of Sense Amplifier-based D Flip- Flop using 0.25 µm and 0.18 µm Technology. Journal of Electronic Design Technology, 4(3), 10-13.

[7]. Blalock, B. J., Li, H. W., Allen, P. E., & Jackson, S. A. (2000). Body-driving as a low-voltage analog design technique for CMOS technology. In Mixed-Signal Design, 2000. SSMSD. 2000 Southwest Symposium on (pp. 113- 118). IEEE.

[8]. Goll, B., & Zimmermann, H. (2009, February). A 65 nm CMOS comparator with modified latch to achieve 7GHz/1.3 mW at 1.2 V and 700MHz/47µW at 0.6 V. In Solid- State Circuits Conference-Digest of Technical Papers, 2009. ISSCC 2009. IEEE International (pp. 328-329). IEEE.

[9]. Johns, D. A., & Martin, K. (2008). Analog Integrated Circuit Design. John Wiley & Sons.

[10]. Maymandi-Nejad, M., & Sachdev, M. (2003). 1-bit quantiser with rail to rail input range for sub-1 V ?S modulators. Electronics Letters, 39(12), 894-895.

[11]. Mesgarani, A., Alam, M. N., Nelson, F. Z., & Ay, S. U. (2010, August). Supply boosting technique for designing very low-voltage mixed-signal circuits in standard CMOS. rd In Circuits and Systems (MWSCAS), 2010 53 IEEE International Midwest Symposium on (pp. 893-896). IEEE.

[12]. Okaniwa, Y., Tamura, H., Kibune, M., Yamazaki, D., Cheung, T. S., Ogawa, J. et al. (2005). A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique. IEEE Journal of Solid-State Circuits, 40(8), 1680-1687.

[13]. Razavi, B. (1995). Principles of Data Conversion System Design (Vol. 126). New York: IEEE Press.

[14]. Savani, V., & Devashrayee, N. M. (2013). Design and Analysis of Source Current effect on Preamplifier-Positive Feedback-based CMOS Comparator using 90 nm Technology. Journal of VLSI Design Tools & Technology, 3(3), 15-26.

[15]. Savani, V., & Devashrayee, N. M. (2014). Performance Analysis and Characterization of Shared Charge and Clocked-Latch based Comparator using 90- nm Technology. Journal of VLSI Design Tools & Technology, 4(3), 20-26.

[16]. Schinkel, D., Mensink, E., Klumperink, E., Van Tuijl, E., & Nauta, B. (2007, February). A double-tail latch-type voltage sense amplifier with 18 ps setup+ hold time. In Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International (pp. 314- 605). IEEE.

Full Article (HTML)

Pdf

Research Paper

Optimization of Microhotplate for Gas Sensing Applications

Manju Ahuja* , B. Prasad, Rajneesh Talwar*

* Research Scholar, I.K.G. Punjab Technical University, Jalandhar, Punjab, India.

Electronic Science Department, Kurukshetra University, Kurukshetra, Haryana, India.

* Principal, CGC Technical Campus, Mohali, Punjab, India.

Ahuja, M., Prasad, B., and Talwar, R. (2017). Optimization of Microhotplate for Gas Sensing Applications. i-manager’s Journal on Electronics Engineering, 7(4), 9-15. https://doi.org/10.26634/jele.7.4.13684

Abstract

With industrial revolution, gas sensors are widely used to measure and monitor traces of environmentally hazardous gases like carbon monoxide, nitrogen dioxide, ammonia, methane, etc. Several gas sensing techniques, include optical sensitive, Surface Acoustic Waves (SAW), Polymers, semiconductor materials, etc. In semiconductor metal oxide, gas sensor activation of oxide sensing layer requires elevated temperature for which microhotplate (MHP) is used. The main objective of this work is to simulate the performance of MHP and optimize its geometry with different materials and losses before fabrication which save time and money. In this paper, electrothermal behavior of high temperature MHP is simulated using Finite Element Analysis (FEA) software COMSOL Multiphysics which saves a lot of time, cost and material before actual fabrication. Simulation result presents the temperature estimation of microheater of Double spiral, S-shape, Meander geometries of PolySilicon and Platinum materials on stack membrane of SiO₂ and Si₃N₄mounted on Silicon substrate. Membrane is having 325 x 325 μm² size and microheater area of 65 x 65 μm² with 0.5 μm² thickness. These microheaters are designed for achieving desired temperature of 750 K with minimum voltage and minimum power consumption for both the materials. Total power consumption in MHP depends on various power losses which effects power efficiency and microheater temperature. Conduction loss in dielectric membrane which contributes as power loss component is calculated for various values of dielectric thickness. Loss linearly increases with dielectric thickness and decrease in microheater temperature and with high mechanical stability of stack. Simulation results shows S-shape is preferred for achieving desired temperature with minimum voltage, however minimum power consumption is for Double spiral shape for both Platinum and Polysilicon materials. Dielectric thickness is optimized for minimum conduction losses for achieving desired temperature.

References

[1]. Chen, W., Zhou, Q., Wan, F., & Gao, T. (2012). Gas sensing properties and mechanism of nano-SnO₂-based sensor for hydrogen and carbon monoxide. Journal of Nanomaterials, 2012, 1.

[2]. Chung, W. Y., Lim, J. W., Lee, D. D., Miura, N., & Yamazoe, N. (2000). Thermal and gas-sensing properties of planar-type micro gas sensor. Sensors and Actuators B: Chemical, 64(1), 118-123.

[3]. Chwieroth, B., Patton, B. R., & Wang, Y. (2001). Conduction and Gas–Surface Reaction Modeling in Metal Oxide Gas Sensors. Journal of Electroceramics, 6(1), 27-41.

[4]. Courbat, J., Canonica, M. D., Briand, D., de Rooij, N. F., Teyssieux, D., Thiery, L., et al. (2008, October). Thermal simulation and characterization for the design of ultra-low power micro-hotplates on flexible substrate. In Sensors, 2008 IEEE (pp. 74-77). IEEE.

[5]. Faleh, R., Othman, M., Gomri, S., Aguir, K., & Kachouri, A. (2016). A transient signal extraction method of WO₃ gas sensors array to identify polluant gases. IEEE Sensors Journal, 16(9), 3123-3130.

[6]. Iwaki, T., Covington, J. A., Gardner, J. W., Udrea, F., Blackman, C. S., & Parkin, I. P. (2006, October). SQI-CMOS based single crystal silicon micro-heaters for gas sensors. In Sensors, 2006. 5^th IEEE Conference on (pp. 460-463). IEEE.

[7]. Kathirvelan, J., Vijayaraghavan, R. (2014). Design, Simulation and Analysis of Platinum Microheater on substrate for sensor applications, ARPAN Journal of Engineering and Applied Sciences, 9, 2307-2314.

[8]. Kumar, H., Singh, K. K., Sood, N., Kumar, A., & Mittal, R. K. (2014, February). Design and simulation of a Micro Hotplate for MEMS based integrated gas sensing system. In Sensors Applications Symposium (SAS), 2014 IEEE (pp. 181-184). IEEE.

[9]. Lee, D. S., Han, S. D., Huh, J. S., & Lee, D. D. (1999). Nitrogen oxides-sensing characteristics of WO₃-based nanocrystalline thick film gas sensor. Sensors and Actuators B: Chemical, 60(1), 57-63.

[10]. Liu, X., Cheng, S., Liu, H., Hu, S., Zhang, D., & Ning, H. (2012). A survey on gas sensing technology. Sensors, 12(7), 9635-9665.

[11]. Maluf, N., & Williams, K. (2004). Introduction to Microelectromechanical Systems Engineering. Artech House.

[12]. Miorandi, D., Sicari, S., De Pellegrini, F., & Chlamtac, I. (2012). Internet of things: Vision, applications and research challenges. Ad Hoc Networks, 10(7), 1497-1516.

[13]. Naumann, F., Ebert, M., Hildenbrand, J., Moretton, E., Peter, C., & Wollenstein, J. (2009, April). Thermal and mechanical design optimisation of a micro machined mid-infrared emitter for optical gas sensing systems. In Thermal, Mechanical and Multi-Physics simulation and Experiments in Microelectronics and Microsystems, 2009. EuroSimE 2009. 10^th International Conference on (pp. 1-5). IEEE.

[14]. Prasad, M., & Khanna, V. K. (2015). A low-power, micromachined, double spiral hotplate for MEMS gas sensors. Microsystem Technologies, 21 (10), 2123-2131.

[15]. Prasad, M., Yadav, R. P., Sahula, V., & Khanna, V. K. (2011). Design and simulation of Pt-based microhotplate, and fabrication of suspended dielectric membrane by bulk micromachining. In 16^th International Workshop on Physics of Semiconductor Devices (Vol. 8549, p. 85491C). International Society for Optics and Photonics.

[16]. Rossi, C., Temple-Boyer, P., & Estève, D. (1998). Realization and per formance of thin SiO2/SiNx membrane for microheater applications. Sensors and Actuators A: Physical, 64(3), 241-245.

[17]. Saxena, G., & Paily, R. (2012, December). Simulation study of power loss components in a microheater. In Power and Energy in NERIST (ICPEN), 2012 1^st International Conference on (pp. 1-5). IEEE.

[18]. Saxena, G., & Paily, R. (2013, June). Effect of membrane to heater ratio on the performance of square microhotplate. In Emerging Research Areas and 2013 International Conference on Microelectronics, Communication sand Renewable Energy (AICERA/ICMiCR), 2013 Annual International Conference on (pp. 1-5). IEEE.

[19]. Saxena, G., & Paily, R. (2015). Choice of insulation materials and its effect on the performance of square microhotplate. Microsystem Technologies, 21(2), 393- 399.

[20]. Singh, A. V. (2015). Fabrication of a Micro-hotplate for Application as an Infrared Emitter (Doctoral Dissertation, Carleton University Ottawa).

[21]. Xu, L., Li, T., Gao, X., & Wang, Y. (2011). Development of a reliable micro-hotplate with low power consumption. IEEE Sensors Journal, 11(4), 913-919.

Full Article (HTML)

Pdf

Research Paper

Design and Analysis of SRAM Cell using Pulsed Latch Circuit in Different CMOS Technologies

N. Namrata* , Khemraj Deshmukh**

* PG Scholar, Department of Electronics and Telecommunication Engineering, SSTC, SSGI (FET), Bhilai, India.

** Assistant Professor, Department of Electronics and Instrumentation Engineering, SSTC, SSGI (FET), Bhilai, India.

Namrata, N., and Deshmukh, K. (2017). Design and Analysis of SRAM Cell using Pulsed Latch Circuit in Different CMOS Technologies. i-manager’s Journal on Electronics Engineering, 7(4), 16-27. https://doi.org/10.26634/jele.7.4.13685

Abstract

In this paper, the authors have designed a 1bit and 8bit SRAM (Static Random Access Memory) cell using pulsed latch circuit in 45 nm, 90 nm, and 180 nm CMOS technologies with 1.0 V,1.2 V and 1.8 V power supply, respectively. The memory cell has become a basic building element in the field of electronic circuit design. The memory cell consists of wide range of applications. It has good specifications due to its large storage capacity, lower access time, and high speed. SRAM cell has become the topic of research due to its increase demand in laptops, memory cards, and in mobile applications for both on-chip and off-chip memories. So, it is very necessary to reduce its power and delay so as to increase its speed. The main aim of this design approach is to reduce power and delay of the SRAM cell. In this design approach, the two NMOS access transistors are replaced by pulsed latch circuit. The pulsed latch circuit consists of 7 transistors in which it has two differential data inputs and a clock signal, also it has two differential data outputs. In this design approach, it is observed that the power and delay is reduced as compared to that of the conventional SRAM cell design. The proposed design has been designed in S-Edit, simulated using T-Spice and their waveform can be viewed in W-Edit. The proposed design has been carried out in Tanner tool v16.0.

References

[1]. Agal, A., Pradeep, & Krishnan, B. (2014). 6T SRAM Cell: Design and Analysis. International Journal of Engineering Research and Applications, 4(3), 574-577.

[2]. Apostolidis, G., Balobas, D., & Konofaos, N. (2016). Design and simulation of 6T SRAM cell architectures in 32nm technology. Journal of Engineering Science and Technology Review, 9(5), 145-149.

[3]. Consoli, E., Alioto, M., Palumbo, G., & Rabaey, J. (2012, February). Conditional push-pull pulsed latches with 726fJ ps energy-delay product in 65 nm CMOS. In Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International (pp. 482-484). IEEE.

[4]. Gopal, M., Prasad, D. S. S., & Raj, B. (2013). 8T SRAM cell design for dynamic and leakage power reduction. International Journal of Computer Applications, 71(9), 43-48.

[5]. Kakde, S. D., Pokle, P. B., & Dorave, J. (2016). Low Power VLSI design Methodologies & Power Management. International Journal of Research in Advent Technology, 4(4), 277-281.

[6]. Kaur, N., Kaur, L., & Kaur, G. (2015). Design and Performance Analysis of Low Power 6T SRAM using Tanner Tool. International Journal of Emerging Engineering Research and Technology, 3(4), 16-21.

[7]. Nikitha, N., & Mutalik, P. (2016). Front end Design of Shift Registers using Latches. International Research Journal of Engineering and Technology, 3(5) , 578-581.

[8]. Partovi, H., Burd, R., Salim, U., Weber, F., DiGregorio, L., & Draper, D. (1996, February). Flow-through latch and edge-triggered flip-flop hybrid elements. In Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42^nd ISSCC., 1996 IEEE International (pp. 138-139). IEEE.

[9]. Sharma, R., Antil, R., & Kumar, K. (2015). Comparitive Study of 6T and 8T SRAM using Tanner Tool. International Journal of Computer Science and Mobile Computing, 4(1), 211-221.

[10]. Stephany, R., Anne, K., Bell, J., Cheney, G., Eno, J., Hoeppner, G., et al. (1998, February). A 200 MHz 32 b 0.5 W CMOS RISC microprocessor. In Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International (pp. 238-239). IEEE.

[11]. Stojanovic, V., & Oklobdzija, V. G. (1999). Comparative analysis of master-slave latches and flipflops for high-performance and low-power systems. IEEE Journal of Solid-State Circuits, 34(4), 536-548.

[12]. Subudhi, T., & Mehra, R. (2014). Design Analysis of CMOS Voltage Mode SRAM Cell using Different nm Technologies. International Journal of Emerging Technologies and Engineering, 1(3), 76-80.

[13]. Tarkasvar, J., Pachori, K. & Jain, R. (2016). Power and Area Optimization of Pulse Latch Shift Register. International Journal of Engineering Research and Development, 12(6), 41-45.

[14]. Tejaswini, N., & Karunashree, B. (2016). VLSI Design of novel RAM using Pulsed Latch based Shift Registers, International Journal of Professional Engineering Studies, 6(3), 120-124.

[15]. Yadav, S., Malik, N., Gupta, A., & Rajput, S. (2013). Low power SRAM design with reduced read/write time. International Journal of Information and Computation Technology, 3(3), 195-200.

[16]. Yang, B. D. (2015). Low-power and area-efficient shift register using pulsed latches. IEEE Transactions on Circuits and Systems I: Regular Papers, 62(6), 1564-1571.

Full Article (HTML)

Pdf

Research Paper

Comparison of Different Designs of Pulse Triggered Flip-Flop based Shift Register at 32nm Technology

Sandeep Kumar* , Khemraj Deshmukh**

* PG Scholar, Department of Electronics and Telecommunication Engineering, SSTC, SSGI (FET), Bhilai, India.

** Assistant Professor, Department of Electronics and Instrumentation Engineering, SSTC, SSGI (FET), Bhilai, India.

Kumar, S., and Deshmukh, K. (2017). Comparison of Different Designs of Pulse Triggered Flip-Flop based Shift Register at 32nm Technology. i-manager’s Journal on Electronics Engineering, 7(4), 28-33. https://doi.org/10.26634/jele.7.4.13686

Abstract

In digital VLSI, sequential elements are most power consuming components. Flip-Flops are the basic storage elements and subsystem of clock distribution network which consume large amount of power. Nowadays for digital design, designers use pipelining techniques to design flip-flop based systems, such as shift registers and register files. In this paper, Pulse Triggered Flip-flop (P-FF) is discussed and Serial in Serial out (SISO) shift register is designed as its application. The main objective of this paper is to optimize the area and power of the shift register for use in Application Specific Integrated Circuits (ASICs) and embedded systems. This paper demonstrates the design of SISO shift registers in three different ways. First shift register is simple in structure and designed only by using P-FF. Second shift register uses clock gating circuit to reduce the switching power consumption and third design of shift register, pulse generator of P-FF is shared among all the latches. These three different SISO shift registers are compared in terms of power dissipation and transistor counts. Shift register has been designed at schematic level and simulated using Tanner EDA at CMOS 32nm BSIM4 technology. The simulation results of SISO shift register with common pulse generator shows effective reduction of power consumption and transistor count.

References

[1]. Benini, L., De Micheli, G., Macii, E., Poncino, M., & Scarsi, R. (1999). Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers. ACM Transactions on Design Automation of Electronic Systems (TODAES), 4(4), 351-375.

[2]. Chandrakasan, A. P., Sheng, S., & Brodersen, R.W. (1992). Low Power CMOS Digital Design. IEEE Journal of Solid-State Circuits, 27(4), 473-483.

[3]. Dev, M. P., Baghel, D., Pandey, B., Pattanaik, M., & Shukla, A. (2013, April). Clock gated low power sequential circuit design. In Information & Communication Technologies (ICT), 2013 IEEE Conference on (pp. 440- 444). IEEE.

[4]. Kang, S. M., Leblebici, Y., & Kim, C. (2014). CMOS Digital Integrated Circuits: Analysis & Design (No. EPFLBOOK- 202021). McGraw-Hill Higher Education.

[5]. Lin, J. F. (2014). Low-Power Pulse-Triggered Flip-Flop Design based on a Signal Feed-through Scheme. IEEE Transaction on Very Large Scale Integration (VLSI) Systems. 22(1), 181-185.

[6]. Luo, S. C., Huang, C. J., & Chu, Y. H. (2013). An adaptive pulse-triggered flip-flop for a high-speed and voltage-scalable standard cell library. IEEE Transactions on Circuits and Systems II: Express Briefs, 60(10), 677-681.

[7]. Shaker, M. O., & Bayoumi, M. A. (2011, May). A clock gated flip-flop for low power applications in 90 nm CMOS. In Circuits and Systems (ISCAS), 2011 IEEE International Symposium on (pp. 558-562). IEEE.

[8]. Shen, J., Geng, L., Xiang, G., & Liang, J. (2014). Lowpower level converting flip-flop with a conditional clock technique in dual supply systems. Microelectronics Journal, 45(7), 857-863.

[9]. Srinivasan, N., Prakash, N. S., Shalakha, D., Sivaranjani, D., & Sundari, B. B. T. (2015). Power Reduction by Clock Gating Technique. Procedia Technology, 21, 631-635.

[10]. Strollo, A. G. M., & De Caro, D. (2000). Low power flipflop with clock gating on master and slave latches. Electronics Letters, 36(4), 294-295.

[11]. Strollo, A. G., Napoli, E., & De Caro, D. (2000, August). New clock-gating techniques for low-power flipflops. In Proceedings of the 2000 International Symposium on Low Power Electronics and Design (pp. 114-119). ACM.

[12]. Tiwari, V., Singh, D., Rajgopal, S., Mehta, G., Patel, R., & Baez, F. (1998, May). Reducing power in highth performance microprocessors. In Proceedings of the 35 Annual Design Automation Conference (pp. 732-737). ACM.

[13]. Tschanz, J., Narendra, S., Chen, Z., Borkar, S., Sachdev, M., & De, V. (2001, August). Comparative delay and energy of single edge-triggered and dual edgetriggered pulsed flip-flops for high-performance microprocessors. In Proceedings of the 2001 International Symposium on Low Power Electronics and Design (pp. 147-152). ACM.

[14]. Wu, Q., Pedram, M., & Wu, X. (2000). Clock-gating and its application to low power design of sequential circuits. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 47(3), 415-420.

[15]. Wu, X., & Pedram, M. (2000, August). Low power sequential circuit design by using priority encoding and clock gating. In Proceedings of the 2000 international Symposium on Low Power Electronics and Design (pp. 143-148). ACM.

Full Article (HTML)

Pdf

Research Paper

Modeling of Hexagonal and Octagonal Photonic Crystal Fiber

Aakash Joshi* , Sharad Mohan Shrivastava, Vikas Sahu*, Anshu****

, PG Scholar, Department of Electronics and Communication Engineering, Shri Shankaracharya Technical Campus, Bhilai, India.

- Assistant Professor, Department of Electronics & Telecommunication Engineering, Shri Shankaracharya Technical Campus, Bhilai, India.

Joshi, A., Shrivastava, S.M., Sahu, V., and Anshu. (2017). Modeling of Hexagonal and Octagonal Photonic Crystal Fiber. i-manager’s Journal on Electronics Engineering, 7(4), 34-40. https://doi.org/10.26634/jele.7.4.13687

Abstract

In this paper, the authors have designed two structures of Photonic crystal fiber. These structures consist of 4 rings of Hexagonal and octagonal air holes. PML and Scattering Boundary condition is applied on these photonic crystal fiber structures. The Finite Element Method of COMSOL Multi Physics is used to design these proposed structures and MATLAB is used to plot the effective refractive index and confinement loss in various cases. It has been observed that the effective refractive index and confinement loss not only varies by change in wavelength, but also by changing the structural parameters of air holes, such as diameter (d) of air holes and pitch (Λ) at 1.55 μm wavelength. The effective area of Hexagonal and Octagonal PCF at 1.55 μm wavelength are 163.45 μm² and 217.425 μm² , respectively.

References

[1]. Amir, A., Revathi, S., Inbathini, S. R., & Chandran, A. (2013). Modeling of Circular Photonic Crystal Fiber Structure for High Non-linearity. International Journal of Advanced Electrical and Electronics Engineering (IJAEEE), 2(3), 88-92.

[2]. Bjarklev, A., Riishede, J., Libori, S. B., & Broen, J. (2002). Photonic cr ystal fibres-novel fibres, new applications. In Transparent Optical Networks, 2002. th Proceedings of the 2002 4 International Conference on (Vol. 2, pp. 172-178). IEEE.

[3]. Bouk, A. H., Cucinotta, A., Poli, F., & Selleri, S. (2004). Dispersion properties of square-lattice photonic crystal fibers. Optics Express, 12(5), 941-946.

[4]. Broeng, J., Barkou, S. E., Bjarklev, A., Knight, J. C., Birks, T. A., & Russell, P. S. J. (1998). Highly increased photonic band gaps in silica/air structures. Optics Communications, 156(4), 240-244.

[5]. Chiang, J. S., & Wu, T. L. (2006). Analysis of propagation characteristics for an octagonal Photonic Crystal Fiber (O-PCF). Optics Communications, 258(2), 170-176.

[6]. Ebendorff-Heidepriem, H., Petropoulos, P., Asimakis, S., Finazzi, V., Moore, R. C., Frampton, K., et al. (2004). Bismuth glass holey fibers with high nonlinearity. Optics Express, 12(21), 5082-5087.

[7]. Ehteshami, N., & Sathi, V. (2012). A novel broadband dispersion compensating square-lattice photonic crystal fiber. Optical and Quantum Electronics, 44(6), 323-335.

[8]. Habib, M. S., Habib, M. S., Razzak, S. A., & Hossain, M. A. (2013). Proposal for highly birefringent broadband dispersion compensating octagonal photoniccrystal fiber. Optical Fiber Technology, 19(5), 461-467.

[9]. Habib, M. S., Habib, M. S., Razzak, S. A., Namihira, Y., Hossain, M. A., & Khan, M. G. (2013). Broadband dispersion compensation of conventional single mode fibers using microstructure optical fibers. Optik- International Journal for Light and Electron Optics, 124(19), 3851-3855.

[10]. Habib, M. S., Nasim, K. M., Habib, M. S., Hasan, M. I., & Ahmad, R. (2013). Relative dispersion slope matched dispersion compensating highly birefringent spiral microstructure optical fibers using defected core. Optical Engineering, 52(9), 096110.

[11]. Jensen, J. B., Riishede, J., Broengx, J., Lægsgaard, J., Larsen, T. T., Sorensen, T., et al. (2003, October). Photonic crystal fibers: Fundamental properties and applications within sensors. In Sensors, 2003. Proceedings of IEEE (Vol. 1, pp. 269-278). IEEE.

[12]. Kaijage, S. F., Namihira, Y., Hai, N. H., Begum, F., Razzak, S. A., Kinjo, T., et al. (2009). Broadband dispersion compensating octagonal photonic crystal fiber for optical communication applications. Japanese Journal of Applied Physics, 48(5R), 052401.

[13]. Knight, J. C., Birks, T. A., Russell, P. S. J., & Atkin, D. M. (1996). All-silica single-mode optical fiber with photonic crystal cladding. Optics Letters, 21(19), 1547-1549.

[14]. Koshiba, M., & Saitoh, K. (2003). Structural dependence of effective area and mode field diameter for holey fibers. Optics Express, 11(15), 1746-1756.

[15]. Li, J., Wang, R., Wang, J., Xu, Z., & Su, Y. (2011, July). Novel large negative dispersion photonic crystal fiber for dispersion compensation. In Mechanic Automation and Control Engineering (MACE), 2011 Second International Conference on (pp. 1443-1446). IEEE.

[16]. Liu, J., Xue, L., Wang, Z., Kai, G., Liu, Y., Zhang, W., & Dong, X. (2006). Large anomalous dispersion at short wavelength and modal properties of a photonic crystal fiber with large air holes. IEEE Journal of Quantum Electronics, 42(9), 961-968.

[17]. Liu, Q., Li, S., & Chen, H. (2015). Two kinds of polarization filter based on photonic crystal fiber with nanoscale gold film. IEEE Photonics Journal, 7(1), 1-11.

[18]. Mishra, S. S., & Singh, V. K. (2011). Study of non-linear properties of hollow core photonic crystal fiber. Optik- International Journal for Light and Electron Optics, 122(8), 687-690.

[19]. Razzak, S. M. A., Namihira, Y., Khan, M. G., Anower, M. S., & Hai, N. H. (2006, December). Transmission characteristics of circular ring pcf and Octagonal PCF: A comparison. In Electrical and Computer Engineering, 2006. ICECE'06. International Conference on (pp. 266- 269). IEEE.

[20]. Russell, P., & Dettmer, R. (2001). A neat idea [photonic crystal fibre]. IEEE Review, 47(5), 19-23.

[21]. Saitoh, K., & Koshiba, M. (2002). Full-vectorial imaginary-distance beam propagation method based on a finite element scheme: Application to photonic crystal fibers. IEEE Journal of Quantum Electronics, 38(7), 927-933.

[22]. Shen, L. P., Huang, W. P., Chen, G. X., & Jian, S. S. (2003). Design and optimization of photonic crystal fibers for broad-band dispersion compensation. IEEE Photonics Technology Letters, 15(4), 540-542.

Full Article (HTML)

Pdf

Research Paper

Variable Staircase Ground Structure Circularly Polarized Microstrip Antenna with an Irregular Slot UHF RFID Reader

Avaneesh Kumar Verma* , Deepam Dubey**

* Department of Electronics Design and Technology, NIELIT, Gorakhpur, India.

** Department of Electronics Design and Technology, NIELIT, Gorakhpur, India.

Verma, A.K., and Dubey, D. (2017). Variable Staircase Ground Structure Circularly Polarized Microstrip Antenna with an Irregular Slot UHF RFID Reader. i-manager’s Journal on Electronics Engineering, 7(4), 41-44. https://doi.org/10.26634/jele.7.4.13688

Abstract

A compact UHF range RFID antenna with Circular Polarization (CP), which is proposed in this paper consists of stair shaped edge with irregular slots on one side and L-shaped feed line on the other. The L-shaped structure improves the Circular Polarization of antenna and provides CP mode at 2.68 GHz under UHF frequency range which is suitable for RFID applications. This antenna also provides bandwidth for RFID reader with -10 dB return loss (reflection coefficient) and have 3 dB axial ratio (AR<3 dB) and impedance bandwidth (VSWR < 2) in the operating frequency band.

References

[1]. Chen, L., Ren, X., Yin, Y., & Wang, Z. (2013). Broadband CPW-fed Circularly Polarized Antenna with an Irregular Slot for 2.45 GHz RFID Reader. Progress in Electromagnetics Research Letters, 41, 77-86.

[2]. Chen, Z. N., Qing, X., & Chung, H. L. (2009). A universal UHF RFID reader antenna. IEEE Transactions on Microwave Theory and Techniques, 57(5), 1275-1282.

[3]. Chi, C. J. (2012). A slot loaded circularly polarized patch antenna for UHF RFID reader. IEEE Transactions on Antennas and Propagation, 60(10), 4516-4521.

[4]. Chung, H. L., Qing, X., & Chen, Z. N. (2007). A broadband circularly polarized stacked probe-fed patch antenna for UHF RFID applications. International Journal of Antennas and Propagation, 2007, 1-9.

[5]. Johnson, J. M., & Rahmat-Samii, V. (1997). Genetic algorithms in engineering electromagnetics. IEEE Antennas and Propagation Magazine, 39(4), 7-21.

[6]. Lo, T. K., Hwang, Y., Lam, E. K. W., & Lee, B. (1997). Miniature aperture-coupled microstrip antenna of very high permittivity. Electronics Letters, 33(1), 9-10.

[7]. Row, J. S., & Ai, C. Y. (2004). Compact design of singlefeed circularly polarised microstrip antenna. Electronics Letters, 40(18), 1093-1094.

[8]. Sharma, P. C., & Gupta, K. C. (1983). Analysis and optimized design of single feed circularly polarized microstrip antennas. IEEE Transactions on Antennas and Propagation, 31(6), 949-955.

[9]. Sze, J. Y., & Pan, S. P. (2011). Design of broadband circularly polarized square slot antenna with a compact size. Progress in Electromagnetics Research, 120, 513- 533.

[10]. Waterhouse, R. B., Targonski, S. D., & Kokotoff, D. M. (1998). Design and performance of small printed antennas. IEEE Transactions on Antennas and Propagation, 46(11), 1629-1633.

i-manager's Journal on Electronics Engineering (JELE)

Current Issue Vol. 15 Issue 1

Most Read

Most Cited

Volume 7 Issue 4 June - August 2017

Analysis and Design of Body Driven Dynamic Latch based Comparator in Low Supply Voltages with nMOS Driver

Vijay Savani* , N. M. Devashrayee**

* Assistant Professor, Department of Electronics and Communication Engineering, Institute of Technology, Nirma University, Gujarat, India. ** Professor, Department of Electronics and Communication Engineering, Institute of Technology, Nirma University, Gujarat, India.

Savani, V., and Devashrayee, N. M. (2017). Analysis and Design of Body Driven Dynamic Latch based Comparator in Low Supply Voltages with nMOS Driver. i-manager’s Journal on Electronics Engineering, 7(4), 1-8. https://doi.org/10.26634/jele.7.4.13683

Abstract

References

Full Article (HTML)

Pdf

Optimization of Microhotplate for Gas Sensing Applications

Manju Ahuja* , B. Prasad**, Rajneesh Talwar***

* Research Scholar, I.K.G. Punjab Technical University, Jalandhar, Punjab, India. ** Electronic Science Department, Kurukshetra University, Kurukshetra, Haryana, India. *** Principal, CGC Technical Campus, Mohali, Punjab, India.

Ahuja, M., Prasad, B., and Talwar, R. (2017). Optimization of Microhotplate for Gas Sensing Applications. i-manager’s Journal on Electronics Engineering, 7(4), 9-15. https://doi.org/10.26634/jele.7.4.13684

Abstract

References

Full Article (HTML)

Pdf

Design and Analysis of SRAM Cell using Pulsed Latch Circuit in Different CMOS Technologies

N. Namrata* , Khemraj Deshmukh**

* PG Scholar, Department of Electronics and Telecommunication Engineering, SSTC, SSGI (FET), Bhilai, India. ** Assistant Professor, Department of Electronics and Instrumentation Engineering, SSTC, SSGI (FET), Bhilai, India.

Namrata, N., and Deshmukh, K. (2017). Design and Analysis of SRAM Cell using Pulsed Latch Circuit in Different CMOS Technologies. i-manager’s Journal on Electronics Engineering, 7(4), 16-27. https://doi.org/10.26634/jele.7.4.13685

Abstract

References

Full Article (HTML)

Pdf

Comparison of Different Designs of Pulse Triggered Flip-Flop based Shift Register at 32nm Technology

Sandeep Kumar* , Khemraj Deshmukh**

* PG Scholar, Department of Electronics and Telecommunication Engineering, SSTC, SSGI (FET), Bhilai, India. ** Assistant Professor, Department of Electronics and Instrumentation Engineering, SSTC, SSGI (FET), Bhilai, India.

Kumar, S., and Deshmukh, K. (2017). Comparison of Different Designs of Pulse Triggered Flip-Flop based Shift Register at 32nm Technology. i-manager’s Journal on Electronics Engineering, 7(4), 28-33. https://doi.org/10.26634/jele.7.4.13686

Abstract

References

Full Article (HTML)

Pdf

Modeling of Hexagonal and Octagonal Photonic Crystal Fiber

Aakash Joshi* , Sharad Mohan Shrivastava**, Vikas Sahu***, Anshu****

*,**** PG Scholar, Department of Electronics and Communication Engineering, Shri Shankaracharya Technical Campus, Bhilai, India. **-*** Assistant Professor, Department of Electronics & Telecommunication Engineering, Shri Shankaracharya Technical Campus, Bhilai, India.

Joshi, A., Shrivastava, S.M., Sahu, V., and Anshu. (2017). Modeling of Hexagonal and Octagonal Photonic Crystal Fiber. i-manager’s Journal on Electronics Engineering, 7(4), 34-40. https://doi.org/10.26634/jele.7.4.13687

Abstract

References

Full Article (HTML)

Pdf

Variable Staircase Ground Structure Circularly Polarized Microstrip Antenna with an Irregular Slot UHF RFID Reader

Avaneesh Kumar Verma* , Deepam Dubey**

* Department of Electronics Design and Technology, NIELIT, Gorakhpur, India. ** Department of Electronics Design and Technology, NIELIT, Gorakhpur, India.

Verma, A.K., and Dubey, D. (2017). Variable Staircase Ground Structure Circularly Polarized Microstrip Antenna with an Irregular Slot UHF RFID Reader. i-manager’s Journal on Electronics Engineering, 7(4), 41-44. https://doi.org/10.26634/jele.7.4.13688

Abstract

References

Full Article (HTML)

Pdf

* Assistant Professor, Department of Electronics and Communication Engineering, Institute of Technology, Nirma University, Gujarat, India.

** Professor, Department of Electronics and Communication Engineering, Institute of Technology, Nirma University, Gujarat, India.

Manju Ahuja* , B. Prasad, Rajneesh Talwar*

* Research Scholar, I.K.G. Punjab Technical University, Jalandhar, Punjab, India.

Electronic Science Department, Kurukshetra University, Kurukshetra, Haryana, India.

* Principal, CGC Technical Campus, Mohali, Punjab, India.

* PG Scholar, Department of Electronics and Telecommunication Engineering, SSTC, SSGI (FET), Bhilai, India.

** Assistant Professor, Department of Electronics and Instrumentation Engineering, SSTC, SSGI (FET), Bhilai, India.

* PG Scholar, Department of Electronics and Telecommunication Engineering, SSTC, SSGI (FET), Bhilai, India.

** Assistant Professor, Department of Electronics and Instrumentation Engineering, SSTC, SSGI (FET), Bhilai, India.

Aakash Joshi* , Sharad Mohan Shrivastava, Vikas Sahu*, Anshu****

, PG Scholar, Department of Electronics and Communication Engineering, Shri Shankaracharya Technical Campus, Bhilai, India.

- Assistant Professor, Department of Electronics & Telecommunication Engineering, Shri Shankaracharya Technical Campus, Bhilai, India.

* Department of Electronics Design and Technology, NIELIT, Gorakhpur, India.

** Department of Electronics Design and Technology, NIELIT, Gorakhpur, India.