i-manager's Journal on Electronics Engineering (JELE)


Volume 7 Issue 4 June - August 2017

Research Paper

Analysis and Design of Body Driven Dynamic Latch based Comparator in Low Supply Voltages with nMOS Driver

Vijay Savani* , N. M. Devashrayee**
* Assistant Professor, Department of Electronics and Communication Engineering, Institute of Technology, Nirma University, Gujarat, India.
** Professor, Department of Electronics and Communication Engineering, Institute of Technology, Nirma University, Gujarat, India.
Savani, V., and Devashrayee, N. M. (2017). Analysis and Design of Body Driven Dynamic Latch based Comparator in Low Supply Voltages with nMOS Driver. i-manager’s Journal on Electronics Engineering, 7(4), 1-8. https://doi.org/10.26634/jele.7.4.13683

Abstract

High speed operation, ultra-low power utilization, and efficiency are the need of battery operated handheld devices. This need forces the use of dynamic latch based comparator, having characteristics of using low supply voltage, high speed, and less power utilization. In this paper, the delay analysis of the body driven p-channel metal oxide semiconductor with a low voltage dynamic comparator is presented. The enhancement in the present structure as suggested by the previous work for fast operation in lower supply voltage is presented. Finally, the modification of the structure is proposed with the help of n-channel metal oxide semiconductor driver based design. Simulation results in 90 nm complementary metal oxide semiconductor technology are carried out for previous work and proposed design. The maximum clock frequency of the modified comparator topology can be achieved up to 500 MHz at a supply voltage of 1 V while consuming 67% less power compared to the previously reported topology.

Research Paper

Optimization of Microhotplate for Gas Sensing Applications

Manju Ahuja* , B. Prasad**, Rajneesh Talwar***
* Research Scholar, I.K.G. Punjab Technical University, Jalandhar, Punjab, India.
** Electronic Science Department, Kurukshetra University, Kurukshetra, Haryana, India.
*** Principal, CGC Technical Campus, Mohali, Punjab, India.
Ahuja, M., Prasad, B., and Talwar, R. (2017). Optimization of Microhotplate for Gas Sensing Applications. i-manager’s Journal on Electronics Engineering, 7(4), 9-15. https://doi.org/10.26634/jele.7.4.13684

Abstract

With industrial revolution, gas sensors are widely used to measure and monitor traces of environmentally hazardous gases like carbon monoxide, nitrogen dioxide, ammonia, methane, etc. Several gas sensing techniques, include optical sensitive, Surface Acoustic Waves (SAW), Polymers, semiconductor materials, etc. In semiconductor metal oxide, gas sensor activation of oxide sensing layer requires elevated temperature for which microhotplate (MHP) is used. The main objective of this work is to simulate the performance of MHP and optimize its geometry with different materials and losses before fabrication which save time and money. In this paper, electrothermal behavior of high temperature MHP is simulated using Finite Element Analysis (FEA) software COMSOL Multiphysics which saves a lot of time, cost and material before actual fabrication. Simulation result presents the temperature estimation of microheater of Double spiral, S-shape, Meander geometries of PolySilicon and Platinum materials on stack membrane of SiO2 and Si3N4 mounted on Silicon substrate. Membrane is having 325 x 325 μm2 size and microheater area of 65 x 65 μm2 with 0.5 μm2 thickness. These microheaters are designed for achieving desired temperature of 750 K with minimum voltage and minimum power consumption for both the materials. Total power consumption in MHP depends on various power losses which effects power efficiency and microheater temperature. Conduction loss in dielectric membrane which contributes as power loss component is calculated for various values of dielectric thickness. Loss linearly increases with dielectric thickness and decrease in microheater temperature and with high mechanical stability of stack. Simulation results shows S-shape is preferred for achieving desired temperature with minimum voltage, however minimum power consumption is for Double spiral shape for both Platinum and Polysilicon materials. Dielectric thickness is optimized for minimum conduction losses for achieving desired temperature.

Research Paper

Design and Analysis of SRAM Cell using Pulsed Latch Circuit in Different CMOS Technologies

N. Namrata* , Khemraj Deshmukh**
* PG Scholar, Department of Electronics and Telecommunication Engineering, SSTC, SSGI (FET), Bhilai, India.
** Assistant Professor, Department of Electronics and Instrumentation Engineering, SSTC, SSGI (FET), Bhilai, India.
Namrata, N., and Deshmukh, K. (2017). Design and Analysis of SRAM Cell using Pulsed Latch Circuit in Different CMOS Technologies. i-manager’s Journal on Electronics Engineering, 7(4), 16-27. https://doi.org/10.26634/jele.7.4.13685

Abstract

In this paper, the authors have designed a 1bit and 8bit SRAM (Static Random Access Memory) cell using pulsed latch circuit in 45 nm, 90 nm, and 180 nm CMOS technologies with 1.0 V,1.2 V and 1.8 V power supply, respectively. The memory cell has become a basic building element in the field of electronic circuit design. The memory cell consists of wide range of applications. It has good specifications due to its large storage capacity, lower access time, and high speed. SRAM cell has become the topic of research due to its increase demand in laptops, memory cards, and in mobile applications for both on-chip and off-chip memories. So, it is very necessary to reduce its power and delay so as to increase its speed. The main aim of this design approach is to reduce power and delay of the SRAM cell. In this design approach, the two NMOS access transistors are replaced by pulsed latch circuit. The pulsed latch circuit consists of 7 transistors in which it has two differential data inputs and a clock signal, also it has two differential data outputs. In this design approach, it is observed that the power and delay is reduced as compared to that of the conventional SRAM cell design. The proposed design has been designed in S-Edit, simulated using T-Spice and their waveform can be viewed in W-Edit. The proposed design has been carried out in Tanner tool v16.0.

Research Paper

Comparison of Different Designs of Pulse Triggered Flip-Flop based Shift Register at 32nm Technology

Sandeep Kumar* , Khemraj Deshmukh**
* PG Scholar, Department of Electronics and Telecommunication Engineering, SSTC, SSGI (FET), Bhilai, India.
** Assistant Professor, Department of Electronics and Instrumentation Engineering, SSTC, SSGI (FET), Bhilai, India.
Kumar, S., and Deshmukh, K. (2017). Comparison of Different Designs of Pulse Triggered Flip-Flop based Shift Register at 32nm Technology. i-manager’s Journal on Electronics Engineering, 7(4), 28-33. https://doi.org/10.26634/jele.7.4.13686

Abstract

In digital VLSI, sequential elements are most power consuming components. Flip-Flops are the basic storage elements and subsystem of clock distribution network which consume large amount of power. Nowadays for digital design, designers use pipelining techniques to design flip-flop based systems, such as shift registers and register files. In this paper, Pulse Triggered Flip-flop (P-FF) is discussed and Serial in Serial out (SISO) shift register is designed as its application. The main objective of this paper is to optimize the area and power of the shift register for use in Application Specific Integrated Circuits (ASICs) and embedded systems. This paper demonstrates the design of SISO shift registers in three different ways. First shift register is simple in structure and designed only by using P-FF. Second shift register uses clock gating circuit to reduce the switching power consumption and third design of shift register, pulse generator of P-FF is shared among all the latches. These three different SISO shift registers are compared in terms of power dissipation and transistor counts. Shift register has been designed at schematic level and simulated using Tanner EDA at CMOS 32nm BSIM4 technology. The simulation results of SISO shift register with common pulse generator shows effective reduction of power consumption and transistor count.

Research Paper

Modeling of Hexagonal and Octagonal Photonic Crystal Fiber

Aakash Joshi* , Sharad Mohan Shrivastava**, Vikas Sahu***, Anshu****
*,**** PG Scholar, Department of Electronics and Communication Engineering, Shri Shankaracharya Technical Campus, Bhilai, India.
**-*** Assistant Professor, Department of Electronics & Telecommunication Engineering, Shri Shankaracharya Technical Campus, Bhilai, India.
Joshi, A., Shrivastava, S.M., Sahu, V., and Anshu. (2017). Modeling of Hexagonal and Octagonal Photonic Crystal Fiber. i-manager’s Journal on Electronics Engineering, 7(4), 34-40. https://doi.org/10.26634/jele.7.4.13687

Abstract

In this paper, the authors have designed two structures of Photonic crystal fiber. These structures consist of 4 rings of Hexagonal and octagonal air holes. PML and Scattering Boundary condition is applied on these photonic crystal fiber structures. The Finite Element Method of COMSOL Multi Physics is used to design these proposed structures and MATLAB is used to plot the effective refractive index and confinement loss in various cases. It has been observed that the effective refractive index and confinement loss not only varies by change in wavelength, but also by changing the structural parameters of air holes, such as diameter (d) of air holes and pitch (Λ) at 1.55 μm wavelength. The effective area of Hexagonal and Octagonal PCF at 1.55 μm wavelength are 163.45 μm2 and 217.425 μm2 , respectively.

Research Paper

Variable Staircase Ground Structure Circularly Polarized Microstrip Antenna with an Irregular Slot UHF RFID Reader

Avaneesh Kumar Verma* , Deepam Dubey**
* Department of Electronics Design and Technology, NIELIT, Gorakhpur, India.
** Department of Electronics Design and Technology, NIELIT, Gorakhpur, India.
Verma, A.K., and Dubey, D. (2017). Variable Staircase Ground Structure Circularly Polarized Microstrip Antenna with an Irregular Slot UHF RFID Reader. i-manager’s Journal on Electronics Engineering, 7(4), 41-44. https://doi.org/10.26634/jele.7.4.13688

Abstract

A compact UHF range RFID antenna with Circular Polarization (CP), which is proposed in this paper consists of stair shaped edge with irregular slots on one side and L-shaped feed line on the other. The L-shaped structure improves the Circular Polarization of antenna and provides CP mode at 2.68 GHz under UHF frequency range which is suitable for RFID applications. This antenna also provides bandwidth for RFID reader with -10 dB return loss (reflection coefficient) and have 3 dB axial ratio (AR<3 dB) and impedance bandwidth (VSWR < 2) in the operating frequency band.