References
[1]. Yang, L. A., Hao, Y., Yu, C. L., & Han, F. Y. (2006). An
improved substrate current model for ultra-thin gate oxide
MOSFETs. Solid-State Electronics, 50(3), 489-495.
[ 2 ] . International technology roadmap for
semiconductor, 2011 retreived from http://public.itrs.net.
[3]. Nicollian, E. H., Brews, J. R., & Nicollian, E. H. (1982).
MOS (metal oxide semiconductor) physics and
technology (Vol. 1987). New York et al.: Wiley.
[4]. S.M. Sze, Physics of semiconductor Devices, Second
ed, John Wiley & Sons, 2003.
[5]. Amin, S. I., Alam, M. S., & Khanam, R. Design
Consideration and Effect of Parameter Variation on sub-
40nm Bulk MOSFET using TCAD Tool. International Journal
of Electronics and Communication Engineering. ISSN,
0974-2166.
[6]. ATLAS Device simulator, SILVACO TCAD software, 2017.
[7]. Sachdeva, N., Vashishath, M., & Bansal, P. K. (2017).
Analytical Modeling & Simulation of OFF-State Leakage
Current for Lightly Doped MOSFETs.
[8]. Gupta, K. A., Anvekar, D. K., & Venkateswarlu, V.
(2013). Modeling of Short Channel MOSFET Devices and
Analysis of Design Aspects for Power Optimisation.
International Journal of Modeling and Optimization, 3(3), 266
[9]. Kloes, A., Schwarz, M., & Holtij, T. (2012). $\hbox
{MOS}^{3}$: A New Physics-Based Explicit Compact
Model for Lightly Doped Short-Channel Triple-Gate SOI
MOSFETs. IEEE Transactions on Electron Devices, 59(2),
349-358.
[10]. Sachdeva, N., Vashishath, M., & Bansal, P. K. (2017).
Effect of Various Parameters on Threshold Voltage of
Virtually Fabricated Lightly Doped PMOS Device. Journal
of VLSI Design Tools & Technology, 7(3), 13-20.
[11]. Ch, A. B., Ravindra, J. V. R., & Lalkishore, K. (2015).
Design of Ultra-Low Power PMOS and NMOS for Nano Scale
VLSI Circuits. Circuits and Systems, 6(03), 60.
[12]. Pradipta Dutta, Binit Syamal, Kalyan Koley, "Shortchannel
drain current model for asymmetric
heavily/lightly doped DG mosfets" Pramana – J. Phys.
(2017) 89:33.
[13]. Persson, K. M., Berg, M., Borg, M. B., Wu, J.,
Johansson, S., Svensson, J., ... & Wernersson, L. E. (2013).
Extrinsic and intrinsic performance of vertical InAs
nanowire MOSFETs on Si substrates. IEEE Transactions on
Electron Devices, 60(9), 2761-2767.
[14]. Mehrotra, S. R., Kim, S., Kubis, T., Povolotskyi, M.,
Lundstrom, M. S., & Klimeck, G. (2013). Engineering
Nanowire n-MOSFETs at $ L_ {g}< 8~{\rm nm}$. IEEE
Transactions on Electron Devices, 60(7), 2171-2177.
