References
[1]. Akbari, M., Maymandi-Nejad, M., & Mirbozorgi, S. A.
(2013, May). A new rail-to-rail ultra low voltage high speed
st comparator. In Electrical Engineering (ICEE), 2013 21
Iranian Conference on (pp. 1-6). IEEE.
[2]. Allen, P. E., & Holberg, D. R. (2002). CMOS Analog
Circuit Design. Oxford Univ. Press.
[3]. Ay, S. U. (2011). A sub-1áVolt 10-bit supply boosted SAR
ADC design in standard CMOS. Analog Integrated Circuits
and Signal Processing, 66(2), 213-221.
[4]. Babayan-Mashhadi, S., & Lotfi, R. (2014). Analysis and
design of a low-voltage low-power double-tail
comparator. IEEE Transactions on Very Large Scale
Integration (VLSI) Systems, 22(2), 343-352.
[5]. Babayan-Mashhadi, S., & Sarvaghad-Moghaddam,
M. (2014, May). Analysis and Design of Dynamic
Comparators in ultra-low supply voltages. In Electrical
nd Engineering (ICEE), 2014 22 Iranian Conference on (pp.
255-258). IEEE.
[6]. Bhatasana, P. M., Savani, V. G., & Mecwan, A. I.
(2013). Implementation of Sense Amplifier-based D Flip-
Flop using 0.25 µm and 0.18 µm Technology. Journal of
Electronic Design Technology, 4(3), 10-13.
[7]. Blalock, B. J., Li, H. W., Allen, P. E., & Jackson, S. A.
(2000). Body-driving as a low-voltage analog design
technique for CMOS technology. In Mixed-Signal Design,
2000. SSMSD. 2000 Southwest Symposium on (pp. 113-
118). IEEE.
[8]. Goll, B., & Zimmermann, H. (2009, February). A 65 nm
CMOS comparator with modified latch to achieve
7GHz/1.3 mW at 1.2 V and 700MHz/47µW at 0.6 V. In Solid-
State Circuits Conference-Digest of Technical Papers,
2009. ISSCC 2009. IEEE International (pp. 328-329). IEEE.
[9]. Johns, D. A., & Martin, K. (2008). Analog Integrated
Circuit Design. John Wiley & Sons.
[10]. Maymandi-Nejad, M., & Sachdev, M. (2003). 1-bit
quantiser with rail to rail input range for sub-1 V ?S
modulators. Electronics Letters, 39(12), 894-895.
[11]. Mesgarani, A., Alam, M. N., Nelson, F. Z., & Ay, S. U.
(2010, August). Supply boosting technique for designing very low-voltage mixed-signal circuits in standard CMOS.
rd In Circuits and Systems (MWSCAS), 2010 53 IEEE
International Midwest Symposium on (pp. 893-896). IEEE.
[12]. Okaniwa, Y., Tamura, H., Kibune, M., Yamazaki, D.,
Cheung, T. S., Ogawa, J. et al. (2005). A 40-Gb/s CMOS
clocked comparator with bandwidth modulation
technique. IEEE Journal of Solid-State Circuits, 40(8),
1680-1687.
[13]. Razavi, B. (1995). Principles of Data Conversion
System Design (Vol. 126). New York: IEEE Press.
[14]. Savani, V., & Devashrayee, N. M. (2013). Design and
Analysis of Source Current effect on Preamplifier-Positive
Feedback-based CMOS Comparator using 90 nm
Technology. Journal of VLSI Design Tools & Technology,
3(3), 15-26.
[15]. Savani, V., & Devashrayee, N. M. (2014).
Performance Analysis and Characterization of Shared
Charge and Clocked-Latch based Comparator using 90-
nm Technology. Journal of VLSI Design Tools & Technology,
4(3), 20-26.
[16]. Schinkel, D., Mensink, E., Klumperink, E., Van Tuijl, E.,
& Nauta, B. (2007, February). A double-tail latch-type
voltage sense amplifier with 18 ps setup+ hold time. In
Solid-State Circuits Conference, 2007. ISSCC 2007.
Digest of Technical Papers. IEEE International (pp. 314-
605). IEEE.