In this paper, the authors have designed a 1bit and 8bit SRAM (Static Random Access Memory) cell using pulsed latch circuit in 45 nm, 90 nm, and 180 nm CMOS technologies with 1.0 V,1.2 V and 1.8 V power supply, respectively. The memory cell has become a basic building element in the field of electronic circuit design. The memory cell consists of wide range of applications. It has good specifications due to its large storage capacity, lower access time, and high speed. SRAM cell has become the topic of research due to its increase demand in laptops, memory cards, and in mobile applications for both on-chip and off-chip memories. So, it is very necessary to reduce its power and delay so as to increase its speed. The main aim of this design approach is to reduce power and delay of the SRAM cell. In this design approach, the two NMOS access transistors are replaced by pulsed latch circuit. The pulsed latch circuit consists of 7 transistors in which it has two differential data inputs and a clock signal, also it has two differential data outputs. In this design approach, it is observed that the power and delay is reduced as compared to that of the conventional SRAM cell design. The proposed design has been designed in S-Edit, simulated using T-Spice and their waveform can be viewed in W-Edit. The proposed design has been carried out in Tanner tool v16.0.