A Study on Globally Asynchronous and locally Synchronous System

Appaneni Srija Chowdary *, M.Bharathi**
* PG Scholar, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College (Autonomous), Tirupati, Andhra Pradesh, India.
** Assistant Professor, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College (Autonomous), Tirupati, Andhra Pradesh, India.
Periodicity:March - May'2018
DOI : https://doi.org/10.26634/jele.8.3.14416


Due to declining technologies and increasing design extent, it is becoming high-priced and troublesome to allocate a global clock signal all through the chip. To overcome this, asynchronous processor design is considered as they do not have global clock. In contrary processor industry makes over a change from synchronous to asynchronous logic. Power and robustness differ notably from synchronous to asynchronous circuits. Synchronous blocks which are communicated by asynchronous links in SoC design is a challenging task. Hence, Globally Asynchronous Locally Synchronous (GALS) system is an appropriate technique, as they merge the advantages of both the Synchronous and Asynchronous approaches. International Technology Roadmap for Semiconductors (ITRS) have detailed that the usage of asynchronous logic doubles by 2024. Asynchronous logic resolves the difficulties that occur in synchronization. Fully Synchronous and GALS are two design approaches to detect a signal in the module of the signal processing system. The primary objective is to demonstrate a low power implementation of GALS system.

The system reduces the large Electro Magnetic Interface (EMI) when an active clock is generating large spikes at the supply current in the synchronous circuit. In order to avoid failures of the synchronous circuits, asynchronous wrappers are used for communication in between the synchronous blocks, where the stability of such systems are to be verified. By using asynchronous wrapper in a synchronous island, one can meet the full design requirements and a single die requires large number of clock frequencies because various IP cores are integrated on a complex systems. An efficient technique to design these kind of distributed SoC is GALS. Some clocking schemes are used here to investigate a number of independent clocks on synchronous domains and to obtain reliable transfer of data and low latency. The efficient systems with hardware complexity, global clock rate reduction, and low power consumption use this kind of technique.


Low Power, Globally Asynochronous Locally Synchronous (GALS), Metastability, Hand Shake Protocol, Latency, Clocking Schemes.

How to Cite this Article?

Chowdary. A. S and Bharathi. M (2018). A Study on Globally Asynchronous and locally synchronous System. i-manager's Journal on Electronics Engineering, 8(3), 26-31. https://doi.org/10.26634/jele.8.3.14416


[1]. Beigne, E., Vivet, P., Thonnart, Y., Christmann, J. F., & Clermidy, F. (2016). Asynchronous circuit designs for the Internet of everything: A methodology for ultra low-power circuits with GALS architecture. IEEE Solid-State Circuits Magazine, 8(4), 39-47.
[2]. Bormann, D. S., & Cheung, P. Y. (1997). Asynchronous wrapper for heterogeneous systems. In Computer Design: VLSI in Computers and Processors, 1997. ICCD'97. Proceedings., 1997 IEEE International Conference on (pp. 307-314). IEEE.
[3]. Chapiro, D. M. (1984). Globally-Asynchronous Locally- Synchronous Systems (No. STAN-CS-84-1026). Stanford Univ CA Dept. of Computer Science. Retrieved from http://www.dtic.mil/dtic/tr/fulltext/u2/a154624.pdf.
[4]. Dasgupta, S., & Yakovlev, A. (2007). Modeling and verification of globally asynchronous and locally synchronous ring architectures. In Design, Automation and Test in Europe, 2005. Proceedings (pp. 568-569). IEEE.
[5]. Heath, M. W., Burleson, W. P., & Harris, I. G. (2005). Synchro-tokens: A deterministic GALS methodology for chip-level debug and test. IEEE Transactions on Computers, 54(12), 1532-1546.
[6]. Hemani, A., Meincke, T., Kumar, S., Postula, A., Olsson, T., Nilsson, P., ... & Lundqvist, D. (1999). Lowering power consumption in clock by using globally asynchronous th locally synchronous design style. In Proceedings of the 36 Annual ACM/IEEE Design Automation Conference (pp. 873-878). ACM.
[7]. Horn, W. (1998). Modelling of an ATM multiplexer in a network terminal for a mixed hardware/ firmware implementation. Retrieved from https://www.researchgate. net/publication/2686869_Modelling_of_an_ATM_Multipl exer_in_a_Network_Terminal_for_a_Mixed_HardwareFirm ware_Implementation
[8]. Jou, S. J., & Chuang, I. Y. (1997). Low-power globally asynchronous locally synchronous design using self-timed circuit technology. In Circuits and Systems, 1997. ISCAS'97., Proceedings of 1997 IEEE International Symposium on (Vol. 3, pp. 1808-1811). IEEE.
[9]. Malley, E., Salinas, A., Ismail, K., & Pileggi, L. (2003). Power comparison of throughput optimized IC busses. In VLSI, 2003. Proceedings. IEEE Computer Society Annual Symposium on (pp. 35-44). IEEE.
[10]. Meincke, T., Hemani, A., Kumar, S., Ellervee, P., Oberg, J., Olsson, T., ... & Tenhunen, H. (1999, July). Globally asynchronous locally synchronous architecture for large high-performance ASICs. In Circuits and Systems, 1999. ISCAS'99. Proceedings of the 1999 IEEE International Symposium on (Vol. 2, pp. 512-515). IEEE.
[11]. Muttersbach, J., Villiger, T., Kaeslin, H., Felber, N., & Fichtner, W. (1999). Globally-asynchronous locallysynchronous architectures to simplify the design of onchip systems. In ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International (pp. 317- 321). IEEE.
[12]. Semiconductor Industry Association. (2009). International Technology Roadmap for Semiconductors. Retrieved from https://www.semiconductors.org
[13]. Villiger, T., Kaslin, H., Gurkaynak, F. K., Oetiker, S., & Fichtner, W. (2003). Self-timed ring for globallyasynchronous locally-synchronous systems. In Asynchronous Circuits and Systems, 2003. Proceedings. Ninth International Symposium on (pp. 141-150). IEEE.
[14]. Yun, K. Y., & Donohue, R. P. (1996). Pausible clocking: A first step toward heterogeneous systems. In Computer Design: VLSI in Computers and Processors, 1996. ICCD'96. Proceedings., 1996 IEEE International Conference on (pp. 118-123). IEEE.
[15]. Zhang, L., Wu, R., & Yang, Y. (2013). A high-speed and low-power synchronous and asynchronous packaging circuit based on standard gates under fourphase one-hot encoding. In Electronic Packaging th Technology (ICEPT), 2013 14 International Conference on (pp. 521-524). IEEE.

Purchase Instant Access

Single Article

North Americas,UK,
Middle East,Europe
India Rest of world
Pdf 35 35 200 20
Online 35 35 200 15
Pdf & Online 35 35 400 25

If you have access to this article please login to view the article or kindly login to purchase the article
Options for accessing this content:
  • If you would like institutional access to this content, please recommend the title to your librarian.
    Library Recommendation Form
  • If you already have i-manager's user account: Login above and proceed to purchase the article.
  • New Users: Please register, then proceed to purchase the article.