i-manager's Journal on Electronics Engineering (JELE)


Volume 9 Issue 4 June - August 2019

Research Paper

High-Speed Double Multiplication Architecture for Parallel Multiplication using Mastrovito Multiplier

Amrutha R.* , U. B. Mahadevaswamy**
*Department of Electronics and Instrumentation Engineering, GSSS Institute of Engineering and Technology for Women, Mysuru, Karnataka, India.
** Department of Electronics and Communication Engineering, Sri Jayachamarajendra College of Engineering, Mysuru, Karnataka, India
Amrutha, R., & Mahadevaswamy, U. B. (2019). High-Speed Double Multiplication Architecture for Parallel Multiplication using Mastrovito Multiplier. i-manager's Journal on Electronics Engineering, 9(4), 1-11. https://doi.org/10.26634/jele.9.4.15284

Abstract

Multiplier is an important unit in ALU to perform arithmetic and logical operations. It should be capable of handling big word length and generate the result in very limited time span. Previous works propose serial bit level multiplication schemes using mastrovito multiplier in which multiplication time and complexity of the circuit increases with increase in number of bits. This paper presents a novel parallel multiplier design architecture for both polynomials and irreducible - nomial with reduced complexity and increased speed. A 64 x 64 multiplier is implemented using mastrovito multiplier and booth encoding technique for multiplication and obtaining partial product, respectively. The implementation is able to achieve reduced complexity, increased speed, and improved accuracy when compared to the existing serial bit level multipliers.

Research Paper

Realization of a Narrow Beamwidth Scanning Technique of a Biological Target in Microwave Tomography

Deborsi Basu* , Kabita Purkait**
*_**Department of Electronics and Communication Engineering, Kalyani Government Engineering College, West Bengal, India.
Basu, D., & Purkait, K. (2019). Realization of a Narrow Beamwidth Scanning Technique of a Biological Target in Microwave Tomography. i-manager's Journal on Electronics Engineering, 9(4), 12-18. https://doi.org/10.26634/jele.9.4.16163

Abstract

In this paper, a realization of a narrow beamwidth scanning approach of a semi-human sized biological target has been done. This approach will be very much helpful for different scanning and image reconstruction techniques used in Microwave Tomography Technique (MTT). Sometimes the difficulty in scanning arises due to the presence of cancerous tumors or affected cells inside the inner regions of human body organ. Identification of the actual region becomes tough using ray analysis techniques. Wide beamwidth scanning makes things more complex. Hence, selection of diagnosis techniques and medicines become difficult. Here, a narrow beamwidth scanning approach has been implemented using a simulation model that can provide a solution to the wide beamwidth scanning problems. A suitable biological human body model has been considered and placed inside a nearfield position in between the transmitter and the receiver. Based on the scanning orientations, the data are collected at the receiver end and analyzed to identify the actual positions of the affected cells inside the model. The output generates satisfactory and accurate results. So, based on this analysis this can be claimed that using the proposed technique in MTT, more accurate diseased cell identification can be done.

Research Paper

Design and Implementation of Solar Powered Automated Garbage Monitoring System

Pushpavathi M. R.* , Shashi Kumar D. M.**, Satish J.***, Sudha K. R.****, Manu D. K.*****
*_***** Department of Electronics and Communication Engineering, K. S. School of Engineering and Management, Bangaluru, Karnataka, India.
Pushpavathi, M. R., Kumar, S. D. M., Satish, J., Sudha, K. R., & Manu, D. K. (2019). Design and Implementation of Solar Powered Automated Garbage Monitoring System. i-manager's Journal on Electronics Engineering, 9(4), 19-24. https://doi.org/10.26634/jele.9.4.14915

Abstract

In modern days, the world has become a very busy place. This is basically due to the rapid increase in population as well as physical resources. Along with these two important factors, there is another factor, which is the total amount of garbage being disposed of. The efficient and practical disposal of garbage is very important with respect to the health of the surrounding environment. The existing methods of garbage collection have been proven inefficient. The proposed system is the smarter way of overcoming the garbage collection and disposal problem. This paper presents the Garbage Collector robot using ARM7. The robot is constructed on a base of size 50 x 40 cm, which is powered by a rechargeable battery of 12 V, 7.5 Ah from the solar panel. The robot movement is controlled by a program in an Android Phone. The robot is designed to collect wet and dry Garbage from every doorstep, by making use of solar energy as a source. While collecting waste it captures the image and stores. The robot is built in such a way that when it starts it will move on the path defined in the program. When it encounters an obstacle, depending on the conditions applied in the program, it stops and later proceeds further motion and then robot picks up the garbage. The main objective of this system is to make sure that the garbage collection, segregation, and disposal is done in a smart and effective way practically. This research work is cost effective and it has a high social impact. This system changes the traditional systems and makes the revolution in waste management. It can automatically monitor the garbage level and sends information to the garbage collection truck. It ultimately helps to keep cleanliness in society.

Research Paper

Design Of Conformal Antenna

P. Jothilakshmi * , N. V. Laxmi Narayen **, G. Lokeshwaran***, K. S. Murugan****
*_****Department of Electronics and Communication Engineering, Sri Venkateswara College of Engineering, Chennai, Tamil Nadu, India.
Jothilakshmi, P., Narayen, N. V. L., Lokeshwaran, G., & Murugan, K. S. (2019). Design Of Conformal Antenna. i-manager's Journal on Electronics Engineering, 9(4), 25-31. https://doi.org/10.26634/jele.9.4.16241

Abstract

The motivation of this paper is to embed the conformal antenna on the surface of the aircraft with increased gain. The most challenging thing in real world is communicating with aircraft, even though several communication technologies have been adopted for tracking and monitoring the aircraft. There is no cent percent efficiency, for that an implementation of conformal antenna for transmission and reception of the signal is preferred. In radio communication and avionics, a conformal antenna or conformal array is a flat radio antenna, which is designed to conform or follow some prescribed shape, for example a curved conformal antenna is designed and is mounted on or embedded in a curved surface. Conformal arrays are typically limited to high frequencies in the UHF or microwave range, where the wavelength of the waves is small enough that small antennas can be used. Requirements for conformal antennas for airborne systems, increased bandwidth requirements, and multi functionality have led to heavy exploitation of printed (patch) or other slot-type antennas and the use of powerful computational tools for designing such antenna. The design and optimization of the conformal antenna can be done through simulation. The proposed antenna provides good radiation and optimal gain and easily embedded to the body of curved shapes.

Research Paper

Implementation of FinFET Based 1-Bit Full Adder

Priti Sahu* , Ravi Tiwari**
*_**Department of Electronics and Telecommunication Engineering, Shri Shankaracharya Group of Institutions, CSVTU, Bhilai, Chattisgarh, India.
Sahu, P., & Tiwari, R. (2019). Implementation of FinFET Based 1-Bit Full Adder. i-manager's Journal on Electronics Engineering, 9(4), 32-42. https://doi.org/10.26634/jele.9.4.16251

Abstract

This paper proposes a 1-bit Full adder using Fin type Field Effect Transistor (FinFET) at 250 nm CMOS technology. The paper is intended to reduce leakage current and leakage power, chip area, Delay and to increase the switching speed of 1-bit Full Adder while maintaining the competitive performance with few transistors used. In this paper, first part implemented Standard CMOS full adder that uses 28 transistors and the next part deals with the implantation a Double-Gate (DG) FinFETs based full adder, which uses 10 transistor count with suitable power consumption, delay performance. and the next part extracting their transfer characteristics by using Synopsys TANNER-EDA simulation tool. The authors investigate the use of Double Gate FinFET technology, which provides low leakage and high-performance operation by utilizing high speed and low threshold voltage transistors for logic cells. It shows that it is particularly effective in subthreshold circuits and can eliminate performance variations with Low power. A 22 ns access time and frequency 0.045 GHz provide 250 nm CMOS process technology with 5 V power supply is employed to carry out 1-bit Full Adder of speed, power, and reliability compared to MOSFET based full adder designs. Hence FinFET is a promising candidate and is a better replacement for MOSFET.