Implementation of FinFET Based 1-Bit Full Adder

Priti Sahu*, Ravi Tiwari**
*_**Department of Electronics and Telecommunication Engineering, Shri Shankaracharya Group of Institutions, CSVTU, Bhilai, Chattisgarh, India.
Periodicity:June - August'2019
DOI : https://doi.org/10.26634/jele.9.4.16251

Abstract

This paper proposes a 1-bit Full adder using Fin type Field Effect Transistor (FinFET) at 250 nm CMOS technology. The paper is intended to reduce leakage current and leakage power, chip area, Delay and to increase the switching speed of 1-bit Full Adder while maintaining the competitive performance with few transistors used. In this paper, first part implemented Standard CMOS full adder that uses 28 transistors and the next part deals with the implantation a Double-Gate (DG) FinFETs based full adder, which uses 10 transistor count with suitable power consumption, delay performance. and the next part extracting their transfer characteristics by using Synopsys TANNER-EDA simulation tool. The authors investigate the use of Double Gate FinFET technology, which provides low leakage and high-performance operation by utilizing high speed and low threshold voltage transistors for logic cells. It shows that it is particularly effective in subthreshold circuits and can eliminate performance variations with Low power. A 22 ns access time and frequency 0.045 GHz provide 250 nm CMOS process technology with 5 V power supply is employed to carry out 1-bit Full Adder of speed, power, and reliability compared to MOSFET based full adder designs. Hence FinFET is a promising candidate and is a better replacement for MOSFET.

Keywords

FinFET, Full Adder, Logic Styles, Tanner-EDA.

How to Cite this Article?

Sahu, P., & Tiwari, R. (2019). Implementation of FinFET Based 1-Bit Full Adder. i-manager's Journal on Electronics Engineering, 9(4), 32-42. https://doi.org/10.26634/jele.9.4.16251

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