Multiplier is an important unit in ALU to perform arithmetic and logical operations. It should be capable of handling big word length and generate the result in very small time span. Previous works propose serial bit level multiplication schemes using mastrovito multiplier in which multiplication time and complexity of the circuit increases with increase in number of bits. This paper presents a novel parallel multiplier design architecture for both polynomials and irreducible wnomial with reduced complexity and increased speed. A 64x64 multiplier is implemented using mastrovito multiplier and booth encoding technique for multiplication and obtaining partial product respectively. The implementation is able to achieve reduced complexity, increased speed and improved accuracy when compared to the existing serial bit level multipliers.