High-Speed Double Multiplication Architecture for Parallel Multiplication using Mastrovito Multiplier

Amrutha R.*, U. B. Mahadevaswamy**
*Department of Electronics and Instrumentation Engineering, GSSS Institute of Engineering and Technology for Women, Mysuru, Karnataka, India.
** Department of Electronics and Communication Engineering, Sri Jayachamarajendra College of Engineering, Mysuru, Karnataka, India
Periodicity:June - August'2019
DOI : https://doi.org/10.26634/jele.9.4.15284

Abstract

Multiplier is an important unit in ALU to perform arithmetic and logical operations. It should be capable of handling big word length and generate the result in very limited time span. Previous works propose serial bit level multiplication schemes using mastrovito multiplier in which multiplication time and complexity of the circuit increases with increase in number of bits. This paper presents a novel parallel multiplier design architecture for both polynomials and irreducible - nomial with reduced complexity and increased speed. A 64 x 64 multiplier is implemented using mastrovito multiplier and booth encoding technique for multiplication and obtaining partial product, respectively. The implementation is able to achieve reduced complexity, increased speed, and improved accuracy when compared to the existing serial bit level multipliers.

Keywords

Booth Encoding, Parallel Multiplier, Polynomial Basis, Bit-Level Multiplier, Mastrovito Multiplier, Doubles Multiplication.

How to Cite this Article?

Amrutha, R., & Mahadevaswamy, U. B. (2019). High-Speed Double Multiplication Architecture for Parallel Multiplication using Mastrovito Multiplier. i-manager's Journal on Electronics Engineering, 9(4), 1-11. https://doi.org/10.26634/jele.9.4.15284

References

[1]. Abdulrahman, E. A. H., & Reyhani-Masoleh, A. (2015). High-speed hybrid-double multiplication architectures using new serial-out bit-level mastrovito multipliers. IEEE Transactions on Computers, 65(6), 1734-1747. https://doi.org/10.1109/TC.2015.2456023
[2]. Almiladi, A. S. (2010). High performance scalable n m mixed-radix-2 serial-serial multipliers for GF (2 ). Journal of Circuits, Systems, and Computers, 19(05), 1089-1107. https://doi.org/10.1142/S0218126610006621
[3]. de Angel, E., & Swartzlander, E. E. (1996, October). Low power parallel multipliers. In VLSI Signal Processing, IX (pp. 199-208). IEEE. https://doi.org/10.1109/VLSISP.1996. 558332
[4]. Diffie, W., & Hellman, M. (1976). New directions in cryptography. IEEE Transactions on Information Theory, 22(6), 644-654. https://doi.org/10.1109/TIT.1976.1055638
[5]. Elguibaly, F. (2000). A fast parallel multiplier-accumulator using the modified Booth algorithm. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 47(9), 902-908. https://doi.org/10. 1109/82.868458
[6]. Elsayed, E., & El-Boghdadi, H. (2014). Area-efficient digit serial–serial two's complement multiplier. Journal of Circuits, Systems, and Computers, 23(07). https://doi.org/ 10.1142/S0218126614500996
[7]. Erdem, S. S., Yanık, T., & Koç, Ç. K. (2006). Polynomial m basis multiplication over GF (2 ). Acta Applicandae Mathematicae, 93(1), 33-55. https://doi.org/10.1007/ s10440-006-9047-0
[8]. Farooqui, A. A., & Oklobdzija, V. G. (1998, May). General data-path organization of a MAC unit for VLSI implementation of DSP processors. In ISCAS'98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No. 98CH36187) (Vol. 2, pp. 260-263). IEEE. https://doi.org/10.1109/ISCAS.1998. 706891
[9]. Hasan, M. A., Namin, A. H., & Negre, C. (2012). Toeplitz matrix approach for binary field multiplication using quadrinomials. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(3), 449-458. https://doi.org/10.1109/TVLSI.2011.2106524
[10]. Hasan, O., & Kort, S. (2007, August). Automated th formal synthesis of Wallace tree multipliers. In 2007 50 Midwest Symposium on Circuits and Systems (pp. 293- 296). IEEE. https://doi.org/10.1109/MWSCAS.2007. 4488591
[11]. Kang, J. Y., & Gaudiot, J. L. (2006). A simple highspeed multiplier design. IEEE Transactions on Computers, 55(10), 1253-1258. https://doi.org/10.1109/TC.2006.156
[12]. Koblitz, N. (1987). Elliptic curve cryptosystems. Mathematics of Computation, 48(177), 203-209. https://doi.org/10.1090/S0025-5718-1987-0866109-5
[13]. Kuang, S. R., Wang, J. P., & Guo, C. Y. (2009). Modified booth multipliers with a regular partial product array. IEEE Transactions on Circuits and Systems II: Express Briefs, 56(5), 404-408. https://doi.org/10.1109/TCSII.2009. 2019334
[14]. Reyhani-Masoleh, A. (2006). Efficient algorithms and architectures for field multiplication using Gaussian normal bases. IEEE Transactions on Computers, 55(1), 34- 47. https://doi.org/10.1109/TC.2006.10
[15]. Reyhani-Masoleh, A., & Hasan, M. A. (2004). Low complexity bit parallel architectures for polynomial basis m multiplication over GF (2 ). IEEE Transactions on Computers, 53(8), 945-959. https://doi.org/10.1109/TC. 2004.47
[16]. Salomon, O., Green, J. M., & Klar, H. (1995). General algorithms for a simplified addition of 2's complement numbers. IEEE Journal of Solid-State Circuits, 30(7), 839- 844. https://doi.org/10.1109/4.391128
[17]. Satyanarayana, J. H., & Nowrouzian, B. (1996). Design and fpga implementation of digit-serial modified booth multipliers. Journal of Circuits, Systems, and Computers, 6(05), 485-501. https://doi.org/10.1142/ S0218126696000339
[18]. Sharma, M. (2011, December). Disposition (reduction) of (negative) partial product for radix 4 Booth's algorithm. In 2011 World Congress on Information and Communication Technologies (pp. 1169-1174). IEEE. https://doi.org/10.1109/WICT.2011.6141414
[19]. Srinivasan, M., & Tamilselvan, G. M. (2017). VLSI implementation of low power high speed ECC processor using versatile bit serial multiplier. Journal of Circuits, Systems and Computers, 26(07). https://doi.org/10.1142/ S0218126617501146
[20]. Wu, H. (2008). Bit-parallel polynomial basis multiplier for new classes of finite fields. IEEE Transactions on Computers, 57(8), 1023-1031. https://doi.org/10.1109/ TC.2008.67
[21]. Yeh, W. C., & Jen, C. W. (2000). High-speed Booth encoded parallel multiplier design. IEEE Transactions on Computers, 49(7), 692-701. https://doi.org/10.1109/12. 863039

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