High-Speed Double Multiplication Architecture for Parallel Multiplication using Mastrovito Multiplier

R. Amrutha*, U. B. Mahadevaswamy**
*Department of Electronics and Instrumentation Engineering, GSSS Institute of Engineering and Technology for Women, Mysuru, Karnataka, India.
** Department of Electronics and Communication Engineering, Sri Jayachamarajendra College of Engineering, Mysuru, Karnataka, India
Periodicity:June - August'2019

Abstract

Multiplier is an important unit in ALU to perform arithmetic and logical operations. It should be capable of handling big word length and generate the result in very small time span. Previous works propose serial bit level multiplication schemes using mastrovito multiplier in which multiplication time and complexity of the circuit increases with increase in number of bits. This paper presents a novel parallel multiplier design architecture for both polynomials and irreducible wnomial with reduced complexity and increased speed. A 64x64 multiplier is implemented using mastrovito multiplier and booth encoding technique for multiplication and obtaining partial product respectively. The implementation is able to achieve reduced complexity, increased speed and improved accuracy when compared to the existing serial bit level multipliers.

Keywords

Booth encoding, parallel multiplier, polynomial basis, bit-level multiplier, Mastrovito multiplier, doubles multiplication.

How to Cite this Article?

Amrutha, R., & Mahadevaswamy, U. B. (2019). High-Speed Double Multiplication Architecture for Parallel Multiplication using Mastrovito Multiplier. i-manager's Journal on Electronics Engineering, 9(4), 1-11.

References

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