An analytical approach to Network with IoT security using NodeMCU access point- Prevention Technique
AUDIO CRYPTOGRAPHY USING AES ALGORITHM TECHNIQUE
ULTRA WIDEBAND TECHNOLOGY
Smart Rover-Voice Control Bluetooth Control Robot to Avoid Obstacles
A Review of Quality Assurance Texture for Highly Pigmented Iris Recognition Using an Optimal Wavelength Band
FEATURE EXTRACTION AND CLASSIFICATION OF DIFFERENT HAND MOVEMENTS FROM THE EMG SIGNAL USING LINEAR DISCRIMINANT ANALYSIS CLASSIFIER
The Impact of Substrate Doping Concentration on Electrical Characteristics of 45nm Nmos Device
A Study on Globally Asynchronous and locally Synchronous System
Performance Analysis of Modified Source Junctionless Fully Depleted Silicon-on-Insulator MOSFET
Method of 2.5 V RGMII Interface I/O Duty Cycle and Delay Skew Enhancement
Automatic Accident Detection and Tracking of Vehicles by Using MEMS
Efficient Image Compression Algorithms Using Evolved Wavelets
Computer Modeling and Simulation of Ultrasonic Signal Processing and Measurements
Effect of Nano-Coatings on Waste-to-Energy (WTE) plant : A Review
ANFIS Controlled Solar Pumping System
FEATURE EXTRACTION AND CLASSIFICATION OF DIFFERENT HAND MOVEMENTS FROM THE EMG SIGNAL USING LINEAR DISCRIMINANT ANALYSIS CLASSIFIER
In this paper, the problem of reducing difference between rise and fall delays (output delay skew) of Input/Outpuut (I/O) cells and duty cycle enhancement to meet 2.5 V Reduced Gigabit Media Independent Interface (RGMII) 2.0 interface I/Os timing requirements at Gigabit Ethernet 125 MHz clock speed was investigated and analyzed. Stacked I/O design specifics (reference voltages and their instability) were considered for example design of 2.5 V I/Os in 28 nm technology with 1.8V dual-gate-oxide (dgo) transistors (Yoshida, 2017). Testbench for test I/O bank Layout Parasitic Extraction (LPE) netlist spice simulations was created in Cadence Virtuoso design environment for I/O rise/fall delays and duty cycle evaluation at bank-level including package Resistor-Inductor-Capacitor (R-L-C) and T-line models, and worst data toggle patterns were used to take simultaneously switching effects into account. Method for connecting decoupling capacitors to reference voltages was used to achieve reduced voltage noise, adjusted rise/fall delays, reduced skew, and output signal stabilized for both single I/O and I/O bank. Analysis was carried out for various values of decoupling capacitors to calculate appropriate one and meet the given RGMII specification timing requirements.
This paper presents design of a microstrip patch antenna with cantilever type Micro-Electro-Mechanical Systems (MEMS) switch to achieve reconfigurability. The primary and secondary radiators are connected by a cantilever MEMS switch. Normally, the MEMS switches are fabricated over high resistive materials whereas planar radiator is designed on low dielectric substrate. Lateral etching based micromachining of Silicon (Si) substrate is proposed in the design to enhance its performance by accommodating a MEMS switch on it. In order to visualize the effect of bandwidth (BW) with respect to the depth of etching, a parametric study was carried out. The simulation results validate the reconfigurability of the design by observing shifts in resonance frequency of 600 MHz by changing the state of MEMS switch.
Indeed, for many industrial applications, precise and reliable monitoring of temperature is significantly important. To ensure this, various temperature sensors such as Thermocouples, Thermistors, Resistance Temperature Detectors (RTDs), Pyrometers, Semiconductor sensors, etc., are readily available. These sensors depict their own salient features. For accurate and reliable temperature monitoring, the monolithic temperature sensors are always recommended. Moreover, it is found that, monolithic temperature sensors demonstrate diversity in sensing mechanism, which results into diversity in the values of the temperature to be monitored. This may result into degradation in reliability of the temperature monitoring system. To explore the details, an embedded system is designed for comparative performance analysis of monolithic temperature sensors, and results of the investigation are presented in this paper.
The multichannel embedded system is developed by deploying the 89S52 microcontroller wherein data acquisition and computing are carried out precisely. Two monolithic temperature sensors; temperature dependent voltage sensor, 0 (LM35: a = 1 mV/ C) and temperature dependent current sensor (AD590 : a = 1 mA/K), have been interfaced. Digital readout (DRO) unit is developed about on a 16X2 Liquid Crystal Display (LCD) module. The Integrated Development Environment (IDE), Keil uVision4, is utilized for the firmware development in C environment. The present monitoring system is scientifically calibrated to the temperature in degree Celsius. Temperature values shown by both temperature sensors are simultaneously recorded and the results are interpreted in this paper.
This paper explores the impact of lightly doped (LD) and heavily doped (HD) substrates on a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with 40 nm Gate length. The influence of varying the p-type substrate doping 15 18 -3 concentration (from 10 to 10 cm ) is investigated in terms of the drain current, substrate current, sub-threshold current, on-off current ratio, sub-threshold swing and threshold voltage. The simulation results show that the lightly doped substrate devices with high work-function (wf) gives improved off-state leakage current. It has also been observed that LD devices have high drain current even on low gate oxide thickness. All the simulation and design work have been done in SILVACO TCAD software.
This paper proposes a design of zig-zag shaped Radio Frequency Micro Electro Mechanical System (RF MEMS) capacitive shunt switch with low spring constant and low activation voltage of the order of 4.7 V. In this design, there are two actuation electrodes and a separate signal line. Both electrodes and signal line are arranged such that, the whole arrangement isolates the Direct Current (DC) static charge and the input operating signal. The switch return-loss in upstate condition and the isolation in down-state condition were found more than 20 dB over a wide frequency band of 18 to 51 GHz.The switch yields insertion loss in up-state and return-loss in down-state condition, lower than 0.5 dB at same frequency band. The simulated results were verified through analytical method and are found to be in close agreement.
This paper presents a compact pentagon shaped monopole microstrip patch antenna, which has been modified to improve its performance. All sides of pentagon patch are truncated and offset feeding is provided to enhance the bandwidth. Defected Ground Structure (DGS) is used which has two rectangular slots of quarter wavelength opposite to each other, and a notch beneath the feedline on the partial ground plane. These slots on the ground plane improves the gain and return loss of the design. The analysis is performed and results are obtained using Ansoft High Frequency Structure Simulator (HFSS). Various parameters which include impedance bandwidth, gain, efficiency, radiation pattern and current distribution of the antenna are studied. The performance of proposed antenna is compared with classical antenna design, both having same operating frequency of 7.4 GHz. Results obtained from the simulation shows impedance bandwidth of 16.65 (3.85-20.5 GHz) GHz, which is 60% enhanced bandwidth as compared to classical antenna, maximum gain of 6.85 dB at 14.35 GHz, peak return loss of -41.6 dB at 7.2 Ghz and good radiation pattern is observed at frequencies of 7.34, 10.4, and 19 GHz. Application of this antenna covers Ultrawide Band (UWB), X Band and Ku Band, and it can be used efficiently for mobile or satellite communication.
In this paper, a parametric study of silicon based PIN diode and Silicon Plated Germanium (SPG) PIN diode is performed th and comparative study is presented. SPG is a germanium diode containing 1/10 width of N+ region doped with silicon. The comparative study is performed on different parameters such as P+ layer and N+ layer concentration, Intrinsic layer thickness, P+ region and N+ region width, and Intrinsic region width. The results obtained from simulation shows that the forward current conduction of SPG PIN diode is greater than silicon device and hence, the resistance offered by SPG is far less than silicon device . The whole work of this paper is done with the help of SILVACO simulator tool.
In this paper, the authors have presented a junctionless Fully Depleted Silicon on Insulator (FDSOI) Metal–Oxide–Semiconductor Field-Effect Transistor (MOSFET) with a source engineering on an intrinsic silicon body, with the purpose to improve I /I ratio of a transistor at low thermal budget process. The proposed device consists of a very ON OFF small region of high doping, over dopingless region of the source. The charge plasma concept is also employed to introduce charge plasma on the source and drain region, by using metal electrodes of appropriate work function. In this way, dopingless region of the source and drain gets electrostatically induced, whereas charge carrier density rises in an already doped region of the source. This makes the proposed device to combine the benefits of modified source fully depleted silicon-on-insulator MOSFET (MS FDSOI MOSFET) (i.e., high I current and I /I ratio) and conventional ON ON OFF junctionless transistors plus the transistors with intrinsic Source/Drain (S/D) regions (i.e., low thermal budget process). The electrical properties of the proposed device are simulated and compared with that of conventional MS FDSOI MOSFET.
