i-manager's Journal on Electronics Engineering (JELE)


Volume 5 Issue 2 December - February 2015

Article

Overview of Polymer based MEMS sensors

T. Sripriya* , V. Jeyalakshmi**
* Research Scholar, Department of Electronics and Communication Engineering, Sathyabama University.
** Professor, Department of Electronics and Communication Engineering, College of Engineering, Chennai.
Sripriya, T. and Jeyalakshmi, V. (2015). Overview of Polymer based MEMS sensors. i-manager's Journal on Electronics Engineering, 5(2), 1-6. https://doi.org/10.26634/jele.5.2.3332

Abstract

The objective of this paper is to present an overview of polymer based sensors, and technologies used for their fabrication. In this paper, the design and fabrication of shear stress sensor, silicon based micro sensor, gas sensor, pressure sensor, polymer filled sensor and Quartz sensor are discussed. Sensors are used to detect and measure a physical property. They indicate the value being measured and are also capable of providing a proper response to any change in the measured physical value. Example of commonly used sensors include Pressure Sensor, Temperature Sensor, Gas Sensor, Humidity Sensor, etc., Microelectromechanical System based sensors are miniaturized in size and their sensing is more accurate and they have a long life.

Research Paper

An SDR Architecture for Linearizing RF Power Amplifier with DPD Technique

Asif Ahmed*
Lecturer, Electrical and Communication Engineering, American International University, Bangladesh
Ahmed, A. (2015). An SDR Architecture for Linearizing RF Power Amplifier with DPD Technique. i-manager's Journal on Electronics Engineering, 5(2), 7-14. https://doi.org/10.26634/jele.5.2.3333

Abstract

In wireless transmission systems, non-ideal response of different functional components along with non linearity of power amplifier plays a major role in degrading the transmitter performance. Several parameters define the performance of a wireless, such as Adjacent Channel Power Ratio (ACPR), Error Vector Magnitude (EVM), spectral mask, etc., and the effect of non-ideal behavior of the transmitter affects these parameters. In many standards, these parameter specifications are defined such that the concern for transmitter linearization is very much relaxed. Standards like Terrestrial Trunked Radio (TETRA) specify strict regulation on these parameters. Therefore, the requirement of linearity is a great challenge for the design of a transmitter, and among these the Digital Pre-distortion (DPD) technique is a wellknown concept. In this paper, an appropriate architecture of SDR is presented for successful operation of the DPD technique. Both signal processing and physical layer architecture may be utilized for complete implementation of the SDR system.

Research Paper

Design and Simulation of RF-MEMS Integrated Reconfigurable Antenna for Wideband Applications

K Nalini* , V.R. Anitha**
* M. Tech Student, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College, Tirupati, India.
** Professor, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College, Tirupati, India.
Nalini, K. , and Anitha, V. R. (2015). Design and Simulation of RF-MEMS Integrated Reconfigurable Antenna for Wideband Applications. i-manager's Journal on Electronics Engineering, 5(2), 15-20. https://doi.org/10.26634/jele.5.2.3334

Abstract

Reconfigurability is the ability to adaptively change the characteristics in an antenna system. In this paper, Radio Frequency-Micro Electro Mechanical Switches (RF-MEMS) are integrated to provide a reconfigurable antenna system that radiates similar patterns over a wide range of frequencies. The different issues encountered during the integration of MEMS switches and the overall system design procedure will be described in this work. The final model will radiate at different frequencies with various radiation patterns. The proposed antenna can be used for the wide band applications in the range of DC to 40 GHz range with reconfigurability.

Research Paper

Bridgeless PFC Implementation Using One CycleControl Technique

K. Prathibha* , M. Vasudeva Reddy **
* Assistant Professor, Department of Electrical and Electronics Engineering, SVCE, Tirupati.
** Associate Professor, Department of Electronics and Communication Engineering, YITS, Tirupati.
Prathibha, K., and Reddy, M.V. (2015). Bridgeless PFC Implementation Using One Cycle Control Technique. i-manager's Journal on Electronics Engineering, 5(2), 21-26. https://doi.org/10.26634/jele.5.2.3335

Abstract

To reduce the rectifier bridge conduction loss, different topologies have been developed. Among these topologies, the bridgeless boost does not require range switch and shows both simplicity and high performance. Without the input rectifier bridge, bridgeless PFC generates less conduction loss as compared to the conventional PFC. Although the circuit structure is simple, the location of the boost inductor on the AC side makes it difficult to sense the AC line voltage and inductor current. At the same time, since the AC side inductor structure makes the output floating regarding the input line, the circuit suffers from high common mode noise. Compared to the average current mode control, one cycle control shows many benefits such as no multiplier requirement, no input voltage sensing requirement, and no inductor current sensing requirement. Therefore, one cycle control gives an attractive solution for the bridgeless PFC circuit. In this paper, One Cycle Control technique is implemented in the bridgeless PFC. By using one cycle control both the voltage sensing and current sensing issues of the bridgeless PFC circuit can be solved. The experimental results show both efficiency improvement and good power factor correction function. At the same time EMI results show that the circuit noise is controllable.

Research Paper

VLSI Modeling Of FM0/Manchester Encoder Using EDML Technique For DSRC Application Systems

P. Lokesh* , V. Thrimurthulu**, L. Mihira Priya***
* PG Scholar, Department of ECE, Chadalawada Ramanamma Engineering College, Tirupati (A.P), India.
** Professor, Department of ECE, Chadalawada Ramanamma Engineering College, Tirupathi (A.P), India.
*** Associate Professor, Department of Elelectronics, St Joseph Degree & PG College, Kingkoti, Hyderabad, India.
Lokesh, P., Thrimurthulu, V., and Priya, L.M. (2015). VLSI Modeling Of FM0/Manchester Encoder Using EDML Technique For DSRC Application Systems. i-manager's Journal on Electronics Engineering, 5(2), 27-33. https://doi.org/10.26634/jele.5.2.3336

Abstract

The aim of this paper is to promote intelligent road and vehicle safety systems in order to control the accident rates and vehicle damages by using Dedicated Short Range Communication (DSRC). The DSRC is of two types: automobile-toautomobile and automobile-to-roadside. In automobile-to-automobile, the DSRC has the ability of message sending and broadcasting among automobiles for safety issues and public information announcement. In this paper, the authors propose a complete simulation model of Dual Mode Logic, (DML) Technique. This method increases the hardware utilization rate from 57.14% to 100% for both FM0 and Manchester encodings being used for the Dedicated Short- Range Communication (DSRC) which is a budding technique to drive the smart transportation system into our daily life with low power digital system designs. The maximum operating frequency is 7GHz and 4GHz for Manchester and FM0 encoding. The on board power consumption is 1133 mW at 3.352 V for Manchester encoding and 1106 mW at 3.352 V for FM0 encoding. The presentation of this paper is evaluates 32nm CMOS technology by utilizing the design simulation Xilinx Vivado tools and layout simulation with extended DML Techniques using Microwind simulator. This paper not only provides a fully reused architecture but also exhibits high performance.

Research Paper

Memory Implementation using Multi Bit Flip-Flop

Palagani Yellappa* , Mareddi Bharathkumar**, Shaik Shabana Azmi***
* ,** M.Tech Student, VLSI, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College, Tirupathi
*** Assistant Professor, VLSI, Department of Electronics and Communication Engineering, Annamacharya Institute of Technology & Sciences, Tirupathi..
Yellappa, P., Bharathkumar, M., and Azmi, S.S. (2015). Memory Implementation using Multi Bit Flip-Flop. i-manager's Journal on Electronics Engineering, 5(2), 34-39. https://doi.org/10.26634/jele.5.2.3337

Abstract

In the digital world memory elements play a vital role. In memory devices the most important factors are Area, Power and Speed. Increased Area and Power consumption of the memory device means reduced device reliability and lifetime. Flip-flops are the basic sequential components used for memory applications. D Flip-flop is one of the most commonly used Flip-flops and delay consumed by clocking is a major part of the whole design. In this paper, the authors analyze the design of Single-Bit Flip-Flop (SBFF i.e. 1-bit) and make a performance comparison over the Multi-Bit Flip-Flop (MBFF i.e. 2-bit, 4-bit, 8-bit, 16-bit and 32-bit). In this paper, the authors design SRAM and DRAM using both SBFF and MBFF in Xilinx Virtex-5 family (XC5VLX50). Designing the memory by using SBFF implies more power consumption. To get the maximum reduction in power and delay an algorithm has been proposed in which SBFFs are replaced with maximum possible MBFF without affecting the performance of the original circuit. These result in favor of Multi-Bit Flip-Flop as reduction of delay such as gate delay and net delay.