Development of a 4-Digit BCD Multiplier Architecture with Similarity Investigator
A Compact Plus Shaped with L-Shaped Slotted Microstrip Patch Antenna for GSM, WLAN, WiMAX, C- and X- Band Applications
Vaccination Identification System using Raspberry Pi
A Compact Wideband Monopole Antenna with DGS for WiMAX/WLAN/5G Applications
Analysis of Carbon Nanotube for Low Power Nano Electronics Applications
The Impact of Substrate Doping Concentration on Electrical Characteristics of 45nm Nmos Device
A Study on Globally Asynchronous and locally Synchronous System
Performance Analysis of Modified Source Junctionless Fully Depleted Silicon-on-Insulator MOSFET
Method of 2.5 V RGMII Interface I/O Duty Cycle and Delay Skew Enhancement
Automatic Accident Detection and Tracking of Vehicles by Using MEMS
Efficient Image Compression Algorithms Using Evolved Wavelets
Computer Modeling and Simulation of Ultrasonic Signal Processing and Measurements
Effect of Nano-Coatings on Waste-to-Energy (WTE) plant : A Review
ANFIS Controlled Solar Pumping System
Smart Agricultural Monitoring and Irrigation System using IoT
This paper discusses about an efficient Test Pattern Generator (TPG) for built-in self-test. This method generates Multiple Single Input Change (MSIC) vectors in a pattern.A reconfigurable Johnson counter and an accumulator is combined to generate a class of minimum transition sequences. The TPG used in this paper is flexible to both the test-per-clock and the test-per-scan schemes. A theory is also explained to represent and analyze the sequences and to extract a class of MSIC sequences. Analysis results shows that the produced MSIC sequences have the favorable features of uniform distribution and low input transition density. The performances of the designed TPGs and the circuits under test with 45 nm are used. Simulation results with ISCAS benchmarks demonstrates that MSIC can save test power and impose no more than 10% overhead for a scan design. It also achieves the target fault coverage without increasing the test length, and also saves power up to 50%.
Wireless Sensor Network can be considered to be energy constrained wireless scenarios, since the sensors are operated for extended periods of time, while relying on batteries that are small, lightweight and inexpensive. Energy constrained wireless application is done with the help of Lookup Table-log-BCJR (LUT-Log-BCJR) architecture. In our existing system the conventional LUT-Log-BCJR architecture have wasteful designs requiring high chip areas and hence high energy consumptions Energy constrained applications. This motivated our proposed System the LUT log BCJR is designed with Clock gating technique achieves low-complexity energy-efficient architecture, which achieves a low area and hence a low energy consumption, and also achieving a low energy consumption has a higher priority than having a high throughput. we use most fundamental Add Compare Select (ACS) operations and It having low processing steps, so that low transmission energy consumption is required and also reduces the overall energy consumption.
Quantum Dot Cellular Automata (QCA) is an emerging nanotechnology in the field of Quantum electronics for the low power consumption and high speed of operational phenomenon. Such type of circuit can be used in many digital applications where CMOS circuits cannot be used due to high leakage and low switching speed. The code converters are the basic units for conversion of data to perform arithmetic operations. A new effective binary to BCD converter design using QuantumDot Cellular Automata is presented in this paper. Compared to the available code converters in VLSI technology, this method of using Quantum dots reduces area and increases switching speed. 3-input Majority gate is the basic and universal gate in QCA design. In accordance with the code converter design using 3-input majority gate logic, a 5-input majority gate logic structure is also used here to design the binary to gray code converter. This replacement improves the speed of the system by reducing number of clock cycles required to produce the output. The simulations are done using Xilinx ISE Design suite to get power and timing analysis.
In this paper, the leakage power and speed performances of extended-true single phase clock and MTCMOS using true single phase clock prescaler are investigated. Based upon this study, MTCMOS technique is implemented in true single phase clock logic DFF design. By using a wired OR logic, only one transistor is used for both mode selection and counting logic system. The working frequency of the counter is enhanced and reduced the critical path between the DFF. Using MTCMOS technique a static leakage power is reduced and the speed performances are improved. The designed counter is compared in term of power consumption using DSCH and Micro wind tools.
This paper focusses on foreground calibration technique. For high speed and high resolution video applications, current steering DAC is preferred. In the large current sources, linearity error is introduced and detected by using two current tunning loops and digital controller. In this paper, Vcm based switching method injected between MUX and DAC to compensate the error which reduces the time of operation. For 12-bit DAC prototype realized 90nm CMOS process,90% gate area reduction current source array is achieved. The measurement result demonstrates that the calibrated converter achieves both DNL and INL less than 1LSB.