References
[1]. J. Yuan and C. Svensson. (1989). High-Speed CMOS
Circuit Techniques. IEEE Journal of Solid-State Circuits, Vol.
24, no. 1, pp. 62–70.
[2]. Z. Deng and A. M. Niknejad. (2010). The Speed-Power
Trade-off in the Design of CMOS True-Single-Phase-Clock
Dividers. IEEE Journal of Solid-State Circuits, Vol. 45, No.
11, pp. 2457–2465.
[3]. J. N. Soares, JR and W. A. M. Van Noije. (1999). A 1.6-
Ghz Dual Modulus Prescaler using the Extended True-
Single Phase Clock CMOS Circuit Technique (E-TSPC). IEEE
Journal of Solid-state circuits, Vol. 34, No. 1, pp.97–102.
[4]. A. Keshavarzi, K. Roy, and C. F. Hawkins. (1997).
Intrinsic Leakage in Low Power Deep Submicron CMOS ICs.
In Proc. International Test Conference, pp. 146– 155.
[5]. S.M. Kang, Y. Leblebici (2003). CMOS Digital
Integrated Circuits Analysis and Design. Third Edition:Tata
McGraw Hill.
[6]. CH.Daya and T.Krishna Moorthy (2012). Design of Low
Power FlipFlop using MTCMOS Technique. International
Journal of Computer Application and Information
Technology, Vol.1, No.1.
[7]. M. V. Krishna, M. A. Do, K. S. Yeo, C. Boon, and W. M.
Lim (2010). Design and Analysis of Ultra Low Power True
Single Phase Clock CMOS 2/3 Prescaler. IEEE Transactions:
Circuits System. I, Reg. Papers, Vol. 57, No. 1,pp. 72–82.
[8]. H. J. M. Veendrick (1984). Short-Circuit Dissipation of
Static CMOS Circuitry and its Impact on the Design of
Buffer Circuits. IEEE Journal of Solid-State Circuits, Vol. SC-
19, No. 4.
[9]. X.-P. Yu, M. A. Do, W. M. Lim, K. S. Yeo, and J. G. Ma
(2006). Design and Optimization of the Extended True
Single-Phase Clock-Based Prescaler. IEEE Transactions: Microwave Theory Techniques, Vol. 54, No. 11, pp.
3828–3835.
[10]. Yin-Tsung Hwang and Jin-Fa Lin (2012). Low Voltage
and Low Power Divide by 2/3 Counter Design using Pass
Transistor Logic Circuit Technique. IEEE Transaction:
Circuits System, I, Reg. Papers, Vol. 20, No. 9, pp.
1063–8210.