Loss Distribution Methodology with a Sense Of Emission Dispatch
Low Power Optimization Technique Based Linear Feedback Shift Register
Leakage Power Reduction Using Multi Modal Driven Hierarchical Power Mode Switches
Validation of IOV chain using OVM Technique
Performance of Continuous and Discontinuous Space Vector Pwm Technique for Open End Winding Induction Motor Drive
Electronic Circuit Design for Electromagnetic Compliance through Problem-Based Learning
Trioinformatics: The Innovative and Novel Logic Notation That Defines, Explains, and Expresses the Rational Application of The Law of Trichotomy for Digital Instrumentation and Circuit Design
Design Of a Novel Gated 5T SRAM Cell with Low Power Dissipation in Active and Sleep Mode
A Two Stage Power Optimized Implantable Neural Amplifier Based on Cascoded Structures
An Efficient Hybrid PFSCL based Implementation of Asynchronous Pipeline
This monograph provides an epistemological rational for the “Multiple Trichotomous Correlation Analysis (identified by the acronym: “MULTRICOR”) post hoc “Triostatistics” (Osler, 2014) test methodology. This paper is part four of the publication entitled, “Trichotomous Charge States: The Novel Trioinformatics Application of Neuroengineering Neuromathematics Notation to Express and Expound Polyphase Electrical Systems and Tri-State Buffers for Digital Circuit Design” that appeared in the Journal on Circuits and Systems. MULTRICOR is an in-depth [Trichotomous Nomographical Variance] statistical procedure for the internal testing of the transformative process of qualitative data into quantitative outcomes through the Tri-Squared Test first introduced in the Journal on Mathematics, and further detailed in the Journal on Educational Technology, Journal on School Educational Technology, and Journal on Educational Psychology. MULTRICOR is an advanced statistical measure that is designed to check the validity and reliability of a Tri-Squared Test that can be used to further verify digital circuit designs. This is a novel approach to advanced statistical post hoc Tri- Squared data analysis. It adds considerable value to the mixed methods approach of research design that involves the holistic combination and comparison of qualitative and quantitative data outcomes. A sequential MULTRICOR mathematical model is provided that illustrates the entire process of advanced statistical Trichotomous inquiry.
In modern CMOS technology, the growing demand of low cost integrated circuit requires RFICs featuring low power consumption, high level integration and high data rates, have become critical in wireless systems at around 10 GHz for emerging applications. By employing silicon-based technology it is possible to design low cost direct conversion receivers targeted at 8 - 40 GHz frequency bands. The main focus is on the design and implementation of a receiver front-end for Ka - band (27 - 40 GHz) applications. The drawbacks of these designs are LO self-mixing and 1/f noise. To overcome these drawbacks, a dual - band receiver is proposed to be designed by adopting a wideband two stage LNA and wideband mixer in a 0.18 μm Bipolar Technology. To suppress the LO self-mixing problems, the sub harmonic mixer is applied to the receiver and by adopting a 3D inductor, IF 3-dB bandwidth can be improved. The designs are modeled in SPICE and verified in HSPICE Synopsys tools.
In present years, reversible logic has attained importance in many applications in the field of Quantum Computing, Nanotechnology, Low Power CMOS Design, Cryptography, etc. Without reversible logic, it is not possible to realize quantum computing. Code converters are combinational circuits which are used in digital systems designed to enhance the security of data and to decrease the hardware complexity. This paper presents a design for the reversible gray to binary code converter circuit. The main aim in the reversible logic design is to minimize the number of reversible gates used and the garbage output produced. The proposed design is compared to the existing designs in terms of parameters such as reversible gates, constant inputs, garbage outputs, and quantum cost.
In this modern era, the challenge for IC designers is to maintain a prolonged battery lifetime in portable devices as power consumption is soaring with increased functionality and operating frequency. Excessive power consumption is the major barrier to the advancement of nanoscale CMOS VLSI circuits. Leakage currents are important sources of power consumption in sub-nanometre regime designs. The main sources of leakage are sub threshold leakage, gate leakage, gate induced drain leakage and junction leakage. Sub threshold leakage is the major contributor of static power and minimizing this component is more important in order to alleviate static power. The portable electronic gadgets like smartphones, tablet computers, etc., generally has much longer stand-by period than the operating period. Therefore an increased stand-by current wastes battery power seriously due to leakage. Power gating techniques help to minimize the leakage currents and increase the performance of integrated circuits. The basic strategy of power gating is to provide two power modes, a sleep mode and an active mode. The goal is to switch between these modes at the appropriate time and in the appropriate manner to maximize power savings while decreasing the impact to performance. This paper gives an overview of power gating techniques for controlling static power dissipation and retaining data in stand by periods.
Operational Transresistance Amplifier (OTRA) is an inherently suitable active building block for analog VLSI applications, since the OTRA is not slew limited in the same fashion as voltage op amps [2]. It can provide a high bandwidth independent of the gain. Hence, it does not suffer from constant gain bandwidth product like voltage op amps circuits [8]. An Operational Transresistance Amplifier (OTRA) based phase detector circuit has been proposed, due to the fact that both input and output terminals of OTRA are characterized by low impedance. The proposed circuit is simple to realize and consists of two OTRA based comparators, a CMOS XOR circuit, buffer and an RC integrator.
