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i-manager's Journal on Circuits and Systems (JCIR)

Current Issue Vol. 11 Issue 2

Voltage Stability and Power Loss Minimization with UPFC using Heuristic and Hybrid Heuristic Methods
Design and Analysis of Voltage Difference Transconductance Amplifier (VDTA) at FINFET CMOS Technology
Efficient Logic Cell Design for Ultralow-Energy Subthreshold Operation in Wearable Biomedical Systems
Design and Optimization of MSI-Enabled Multi-Precision Binary Multiplier Architecture
Analysis of Carbon Nanotube for Low Power Nano Electronics Applications

Most Cited

Volume 4 Issue 1 December - February 2016 [Open Access]

Research Paper

Multricor [“Multiple Trichotomous Correlation”Analysis]: The Post Hoc Examination and Measurement of Statistically Significant Tri–Squared Tests to Determine the Total and Internal Strength of Relationships between Trichotomous Variables Used For Dynamic Psychometric Circuit Assessment

James Edward Osler II*

Faculty Member, Department of Curriculum and Instruction, North Carolina Central University (NCCU) School of Education, USA.

Osler, J. E., II. (2016). Multricor [“Multiple Trichotomous Correlation” Analysis]: The Post Hoc Examination and Measurement of Statistically Significant Tri–Squared Tests to Determine the Total and Internal Strength of Relationships between Trichotomous Variables Used For Dynamic Psychometric Circuit Assessment. i-manager’s Journal on Circuits and Systems, 4(1), 1-11. https://doi.org/10.26634/jcir.4.1.6029

Abstract

This monograph provides an epistemological rational for the “Multiple Trichotomous Correlation Analysis (identified by the acronym: “MULTRICOR”) post hoc “Triostatistics” (Osler, 2014) test methodology. This paper is part four of the publication entitled, “Trichotomous Charge States: The Novel Trioinformatics Application of Neuroengineering Neuromathematics Notation to Express and Expound Polyphase Electrical Systems and Tri-State Buffers for Digital Circuit Design” that appeared in the Journal on Circuits and Systems. MULTRICOR is an in-depth [Trichotomous Nomographical Variance] statistical procedure for the internal testing of the transformative process of qualitative data into quantitative outcomes through the Tri-Squared Test first introduced in the Journal on Mathematics, and further detailed in the Journal on Educational Technology, Journal on School Educational Technology, and Journal on Educational Psychology. MULTRICOR is an advanced statistical measure that is designed to check the validity and reliability of a Tri-Squared Test that can be used to further verify digital circuit designs. This is a novel approach to advanced statistical post hoc Tri- Squared data analysis. It adds considerable value to the mixed methods approach of research design that involves the holistic combination and comparison of qualitative and quantitative data outcomes. A sequential MULTRICOR mathematical model is provided that illustrates the entire process of advanced statistical Trichotomous inquiry.

References

[1]. Apostol, T. M. (1967). Calculus, Second Edition, Volume One: One-variable Calculus, with an Introduction to Linear Algebra. Waltham, MA: Blaisdell.

[2]. Kant, I. (2007). Critique of Pure Reason (based on Max Müller's Translation). P. Classics a Division of Pearson PLC. New York, NY.

[3]. Osler, J. E. (2012a). “Trichotomy-Squared - A novel mixed methods test and research procedure designed to analyze, transform, and compare qualitative and quantitative data for education scientists who are administrators, practitioners, teachers, and technologists”. i-manager Journal on Mathematics, Vol. 1, No. 3, pp. 23–31.

[4]. Osler, J. E. and Waden, C. (2012b). “Using innovative technical solutions as an intervention for at risk students: A meta–cognitive statistical analysis to determine the impact of ninth grade freshman academies, centers, and center models upon minority student retention and achievement”. i-manager Journal on School Educational Technology, Vol. 7, No. 3, pp. 11–23.

[5]. Osler, J. E. (2013a). “The psychometrics of educational science: Designing trichotomous inventive investigative instruments for qualitative and quantitative for inquiry”. imanager Journal on Educational Psychology, Vol. 8, No. 3, pp. 15-22.

[6]. Osler, J. E. (2013b). “The psychological efficacy of education as a science through personal, professional, and contextual inquiry of the affective learning domain”. imanager Journal on Educational Psychology, Vol. 6, No. 4, pp. 36-41.

[7]. Osler, J. E. (2013c). “Algorithmic triangulation metrics for innovative data transformation: Defining the application process of the tri-squared test”. i-manager Journal on Mathematics, Vol. 2, No. 2, pp. 10-16.

[8]. Osler, J. E. (2014). “Triostatistics: The application of innovative in-depth advanced post hoc statistical metrics for the assessment and analysis of statistically significant trisquared test outcomes”. Kentucky Journal of Excellence in College Teaching and Learning, Vol. 12, No. 3, pp. 27-39.

[9]. Rust, J. and Golombok, S. (1989). Modern Psychometrics: The Science of Psychological Assessment nd (2 ed.). Florence, KY, US: Taylor & Frances/Routledge.

[10]. Sensagent, (2012). Retrieved, on May 9, 2012 from http://dictionary.sensagent.com/trichotomy+(mathemati cs)/en-en/

[11]. Singh, S. (1997). Fermat’s Enigma: The Epic Quest to Solve the World’s Greatest Mathematical Problem. A. Books a Division of Random House. New York, NY.

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Research Paper

Design of Wideband Sub-Harmonic Receiver Front-End Using 0.18µm CMOS Technology

K. Rajesh* , K. Neelima**

* PG Scholar, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College, Rangampet, Tirupati, India.

** Assistant Professor, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College, Rangampet, Tirupati, India.

Rajesh, K., and Neelima, K. (2016). Design of Wideband Sub-Harmonic Receiver Front-End Using 0.18µm CMOS Technology. i-manager’s Journal on Circuits and Systems, 4(1), 12-15. https://doi.org/10.26634/jcir.4.1.6030

Abstract

In modern CMOS technology, the growing demand of low cost integrated circuit requires RFICs featuring low power consumption, high level integration and high data rates, have become critical in wireless systems at around 10 GHz for emerging applications. By employing silicon-based technology it is possible to design low cost direct conversion receivers targeted at 8 - 40 GHz frequency bands. The main focus is on the design and implementation of a receiver front-end for Ka - band (27 - 40 GHz) applications. The drawbacks of these designs are LO self-mixing and 1/f noise. To overcome these drawbacks, a dual - band receiver is proposed to be designed by adopting a wideband two stage LNA and wideband mixer in a 0.18 μm Bipolar Technology. To suppress the LO self-mixing problems, the sub harmonic mixer is applied to the receiver and by adopting a 3D inductor, IF 3-dB bandwidth can be improved. The designs are modeled in SPICE and verified in HSPICE Synopsys tools.

References

[1]. Ping-Yi Wang, Te-Lin Wu, Min-Chih Chou, Ming-Yu Chen, Yin-Cheng Chang, Da-Chiang Chang, and Shawn S. H. Hsu, (2015). “Design of Wideband Sub-Harmonic Receiver Front-End Using 0.18-µm BiCMOS Technology”. Wireless Symposium (IWS), 2015 IEEE International, pp. 1-4.

[2]. M. El-Nozahi, E. Sanchez-Sinencio, and K. Entesari, (2010). “A millimeter wave (23-32 GHz) wideband BiCMOS low-noiseamplifier”. IEEE J. Solid-State Circuits, Vol. 45, No.2, pp. 289-299.

[3]. L. Sheng, J. C. Jensen, and L. E. Larson, (2000). “A widebandwidth Si/SiGeHBT direct conversion sub harmonic mixer/downconverter”. IEEE J. Solid-State Circuits, Vol. 35, No. 9, pp. 1329-1337.

[4]. Y. H. Chen, H. H. Hsieh, and L. H. Lu, (2008). “A 24-GHz Receiver Front-end with an LO Signal Generator in 0.18-mm CMOS”. IEEE Trans. Microw. Theory Techn., Vol. 56, No. 5, pp. 1043-1051.

[5]. W. Kluge, F. Poegel, H. Roller, M. Lange, T. Ferchland, L. Dathe, and D. Eggert, (2006). “A fully integrated 2.4-GHz IEEE 802.15.4-compliant transceivers for ZigBeeTM applications”. IEEE J. Solid-State Circuits, Vol. 41, No. 12, pp. 2767-2775.

[6]. M. El-Nozahi, E. Sanchez-Sinencio, and K. Entesari, (2010). “A millimeter wave (23-32 GHz) wideband BiCMOS low-noise amplifier”. IEEE J. Solid-State Circuits, Vol. 45, No. 2, pp. 289-299.

[7]. M. El-Nozahi, E. Sanchez-Sinencio, and K. Entesari, (2010). “A 20-32 GHz wideband mixer with 12-GHz IF bandwidth in 0.18 m SiGe process”. IEEE Trans. Microw. Theory Techn., Vol. 58, No. 11, pp. 2731-2740.

[8]. P. Y. Wang, Y. C. Shen, M. C. Chou, Y. C. Chang, T. L. Wu, D.C. Chang, and S. H. Hsu, (2015). “Design of fully integrated receiver front-end for VSAT Applications”. In IEEE 15th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), pp. 11-13.

[9]. C. Cho, and S. H. Hsu, (2010). “A ultra-low-power 24 GHz low-noise amplifier using 0.13m CMOS technology”. IEEE Microw. and Wireless Compont Lett., Vol. 20, No. 12, pp. 681-683.

[10]. J. S. Syu, C. C. Meng, Y. H. Teng, and H.-Y. Liao, (2010). “Large improvement in image rejection of doublequadrature dual-conversion low-IF architectures”. IEEE Trans. Microw. Theory Techn., Vol. 58, No. 7, pp. 1703-1712.

[11]. R. M. Kodkani and L. E. Larson, (2008). “A 24 GHz CMOS passive subharmonic mixer/downconverter for zero- IF applications”. IEEE Trans. Microw. Theory Techn., Vol. 56, No. 5, pp. 1247-1256.

[12]. F. Bruccoleri, E. A. M. Klumperink, and B. Nauta, (2004). “Wideband CMOS Low-Noise Amplifier Exploiting Thermal Noise Cancelling”. IEEE J. Solid-State Circuits, Vol. 39, No. 2, pp. 275-281.

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Research Paper

Efficient Realization of Reversible Gray to Binary Code Converter Circuit

Gowthami P.*

Research Scholar, Department of Electronics and Communication Engineering, S V University College of Engineering, Tirupati, Andhra Pradesh, India.

Gowthami P. (2016). Efficient Realization of Reversible Gray to Binary Code Converter Circuit. i-manager’s Journal on Circuits and Systems, 4(1), 16-19. https://doi.org/10.26634/jcir.4.1.6031

Abstract

In present years, reversible logic has attained importance in many applications in the field of Quantum Computing, Nanotechnology, Low Power CMOS Design, Cryptography, etc. Without reversible logic, it is not possible to realize quantum computing. Code converters are combinational circuits which are used in digital systems designed to enhance the security of data and to decrease the hardware complexity. This paper presents a design for the reversible gray to binary code converter circuit. The main aim in the reversible logic design is to minimize the number of reversible gates used and the garbage output produced. The proposed design is compared to the existing designs in terms of parameters such as reversible gates, constant inputs, garbage outputs, and quantum cost.

References

[1]. Landauer, R. (1961). “Irreversibility and heat generation in the computing process”. IBM Journal of Research and Development, Vol. 5, No. 3, pp.183-191.

[2]. Bennett, C.H, (1973). “Logical reversibility of Computation”. IBM Journal of Research and Development, Vol. 17, No. 6, pp.525-532.

[3]. Feynman, R. (1985). “Quantum Mechanical Computers”. Optics News, Vol. 11, No. 2, pp. 11-20.

[4]. Parhami, B. (2006). “Fault Tolerant Reversible Circuits”. th Proc. 40 Asilomar Conf. Signals, Systems, and Computers, Pacific Grove, CA, pp. 1726-1729.

[5]. Toffoli, T. (1980). Reversible computing. Technical Memo MIT/LCS/TM-151, MIT Lab. for Computer Science.

[6]. Saravanan, and M. Suresh Manic, K. (2013). “Energy Efficient Code Converters using Reversible Logic Gates”. International Conference on Green High Performance Computing, IEEE, pp. 1-6.

[7]. Kotaiah Kamani, Sandeep Koneti, Ujwala Bollampalli, and Sreevanishankara, (2014). “Energy Efficient Reversible logic Design for Code Converters”. ICETET, International Journal of Research and Applications, Vol. 1, No. 3, pp. 132-136.

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Research Paper

Power Gating Techniques for Leakage Reduction in CMOS Circuits - A Brief Survey

M. Kavitha* , T. Govindaraj**

* Assistant Professor, Department of Electronics and Communication Engineering, Government College of Engineering, Bargur, India.

** Professor, Department of Electrical and Electronics Engineering, VSB Engineering College, Karur, India.

Kavitha, M. and Govindaraj, T. (2016). Power Gating Techniques for Leakage Reduction in CMOS Circuits - A Brief Survey. i-manager’s Journal on Circuits and Systems, 4(1), 20-26. https://doi.org/10.26634/jcir.4.1.6032

Abstract

In this modern era, the challenge for IC designers is to maintain a prolonged battery lifetime in portable devices as power consumption is soaring with increased functionality and operating frequency. Excessive power consumption is the major barrier to the advancement of nanoscale CMOS VLSI circuits. Leakage currents are important sources of power consumption in sub-nanometre regime designs. The main sources of leakage are sub threshold leakage, gate leakage, gate induced drain leakage and junction leakage. Sub threshold leakage is the major contributor of static power and minimizing this component is more important in order to alleviate static power. The portable electronic gadgets like smartphones, tablet computers, etc., generally has much longer stand-by period than the operating period. Therefore an increased stand-by current wastes battery power seriously due to leakage. Power gating techniques help to minimize the leakage currents and increase the performance of integrated circuits. The basic strategy of power gating is to provide two power modes, a sleep mode and an active mode. The goal is to switch between these modes at the appropriate time and in the appropriate manner to maximize power savings while decreasing the impact to performance. This paper gives an overview of power gating techniques for controlling static power dissipation and retaining data in stand by periods.

References

[1]. Y. Taur, (2002). “CMOS design near the limit of scaling”. IBM J. Res. & Dev., Vol. 46, No. 2.3, pp. 213-222.

[2]. Jan M. Rabaey, (1996). Digital Integrated Circuits: A Design Perspective. Prentice Hall, USA.

[3]. J. Kao, T. Narendra, G. Siva and Chandrakasan, (2002). “Sub threshold leakage modeling and reduction techniques”. In Proc. IEEE/ACM Conf. CAD, pp. 141-148.

[4]. M. Keating, D. Flynn, R. Aitken, A. Gibsons and K. Shi, (2007). Low Power Methodology Manual for System on Chip Design. Springer Publications, New York.

[5]. K. Roy and Sharat C. Prasad, (2007). Low-Power CMOS VLSI Circuit Design. John Wiley, India.

[6]. N. Weste and David Harris, (2010). CMOS VLSI Design: A Circuits and Systems Perspective. Addison Wesley Publications.

[7]. W. Liao, J.M. Basile and Lei He, (2002). “Leakage power modeling and reduction with data retention”. In Proc. IEEE/ACM Int. Conf. CAD, pp. 714-719.

[8]. H. Singh, Ann Arbor, K. Agarwal, D. Sylvester and K.J. Nowka, (2007). “Enhanced leakage reduction techniques using intermediate strength power gating”. IEEE Trans. VLSI Sys., Vol. 15, No.11, pp. 1215-1224.s

[9]. M. Kavitha and T. Govindaraj, (2015). “Low leakage charge recycling power gating structure for CMOS VLSI circuits”. Inf. MIDEM – J. Microelect. Elect. Comp.& Mat., Vol. 45, No. 1, pp. 66-72.

[10]. M. Kavitha and T. Govindaraj, (2016a). “Low power multimodal switch for leakage reduction and stability improvement in SRAM cell”. Ara. J. Sci. & Engg., Vol. 41, No. 8, pp. 2945-2955.

[11]. M. Kavitha and T. Govindaraj, (2016b). “Low leakage power gating technique for subnanometer CMOS circuits”. Tur. J. Elect. Engg. & Comp. Sci., (In Press).

[12]. M. Kavitha and T. Govindaraj, (2016c). “Power gating technique for power reduction and data retention in CMOS circuits”. J. Elect. Electro. Engg., Vol. 9, pp. 19-24.

[13]. H. Jiang, Marek-Sadowska and S.R. Nassif, (2005). “Benefits and costs of power-gating technique”. In Proc. IEEE Int. Conf. CD: VLSI CAP, pp. 559-566.

[14]. P. Huang, Z. Xing , T. Wang and Qiang Wei, (2010). “A th brief survey on power gating Design”. In Proc. 10 IEEE Int. Conf. SSICAT, pp. 788-790.

[15]. R. Lorenzo and S. Chaudhary, (2013). “A novel all NMOS leakage feedback with data retention technique”. In Proc.IEEE Int. Conf. on CARES., pp.1-5.

[17]. S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigemitsu and J. Yamada, (1995). “1-V Power Supply high-speed digital circuit technology with multi threshold-voltage CMOS”. IEEE J. Solid-State Ckts., Vol. 30, No. 8, pp. 847-854.

[19]. M. H. Chowdhury, J. Gjanci and P. Khaled, (2008). “Controlling ground bounce noise in power gating scheme for system-on-a-Chip”. In Proc. IEEE Comput. Soc. Annu. Symp. VLSI, pp. 437–440.

[21]. H.Jiao and V.Kursun, (2011). “Ground bouncing noise suppression techniques for data preserving sequential MTCMOS circuits”. IEEE Trans. VLSI Sys., Vol. 19, No. 5, pp. 763-773.

[22]. Tada, H. Notani and M. Numa, (2006). “A novel power gating scheme with charge recycling”. IEICE Elect. Exp., Vol. 12, pp. 281-286.

[23]. E. Pakbaznia and M. Pedram, (2012). “Design of a tri- modal multi-threshold CMOS switch with application to data retentive power gating”. IEEE Trans. on VLSI Sys., Vol.20, No. 2, pp. 380-385.

[24]. Z. Liu and V. Kursun, (2007). “Low Energy MTCMOS with th sleep transistor charge recycling”. In Proc. 50 Midwest Symp. on CAS, pp. 891-894.

[25]. W. Zhao and Y. Cao, (2006). “New generation of predictive technology model for sub-45nm early design exploration”. IEEE Trans. on Elect. Dev., Vol. 53, pp. 2816-2823.

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Research Paper

OTRA Based Phase Detector Design

Mamatha Malisetty* , C. V. Sudhakar**

* PG Scholar, Department of VLSI, Sree Vidyanikethan Engineering College, Tirupathi, India.

** Assistant Professor, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College, Tirupathi, India.

Mamatha, M. and Sudhakar, C.V. (2016). OTRA Based Phase Detector Design. i-manager’s Journal on Circuits and Systems, 4(1), 27-33. https://doi.org/10.26634/jcir.4.1.6033

Abstract

Operational Transresistance Amplifier (OTRA) is an inherently suitable active building block for analog VLSI applications, since the OTRA is not slew limited in the same fashion as voltage op amps [2]. It can provide a high bandwidth independent of the gain. Hence, it does not suffer from constant gain bandwidth product like voltage op amps circuits [8]. An Operational Transresistance Amplifier (OTRA) based phase detector circuit has been proposed, due to the fact that both input and output terminals of OTRA are characterized by low impedance. The proposed circuit is simple to realize and consists of two OTRA based comparators, a CMOS XOR circuit, buffer and an RC integrator.

References

[1]. B. Razavi, (2002). “Challenges in the Design of High- Speed Clock and Data Recovery Circuits”. IEEE Comm. Mag., Vol. 40, No. 8, pp. 94-101.

[2]. K. N. Salama and A. M. Soliman, (1999). “CMOS operational transresistance amplifier for analog signal processing applications”. Microelectron. J., Vol. 30, No. 3, pp. 235-245.

[3]. K. Watanabe, M. Madihian, and T. Yamamoh, (1980). “A Cascade Phase Sensitive Detector: Phase Response”. IEEE Trans. Instrum. Meas., Vol. 29, No. 1, pp. 3-6.

[4]. H. Mostafa and A. M. Soliman, (2006). “A modified CMOS realization of the operational transresistance amplifier (OTRA)”. Frequenz, Vol. 60, No. 3-4, pp. 70–76.

[5]. S. Soliman, F. Yuan, and K. Raahemifar, (2002). “An overview of design techniques for CMOS phase detectors”. In Proc. IEEE Int. Symp.Circuits Syst. (ISCAS'02), Vol. 5, pp. 457–460.

[6]. Rajeev Ranjan, Rajeshwari Pandey, Neeta Pandey, and Gavendra Singh, (2015). “Linear Phase Detector Using OTRA”. IEEE International Conference on Signal Processing and Integrated Netwoks, pp. 917-920.

[7]. H.O. Elwan and A.M. Soliman, (1996). “CMOS differential current conveyors and applications for analog VLSI”. Analog Integrated Circuits and Signal Processing, Vol. 11, pp. 35-45.

[8]. H.O. Elwan, A. M. Soliman, and M. Ismail, (2001). “A CMOS Norton amplifier based digitally controlled VGA for low power wireless applications”. IEEE Trans. Circuits Syst. II, Vol. 48, No. 3, pp. 245-254.

[9]. J. Savoj and B. Razavi, “A 10-Gb/s CMOS Clock and Data Recovery Circuit with a Half Rate Linear Phase Detector”. IEEE J. Solid-State, Vol. 36, No. 5, pp. 761-768.

[10]. J. E. Rogers and J. R. Long, (2002). “A 10-Gb/s CDR/DEMUX with LC Delay Line VCO in 0.18-µm CMOS”. IEEE J. of Solid-State Circuits, Vol. 37, No. 12, pp. 1781- 1789.

[11]. A. Rezayee, and K. Martin, (2003). “A 9-16Gb/s clock and data recovery circuit with three-state phase detector and dual-path loop architecture”. 2003 European Solid- State Circuits Conference: Conference Proceedings, pp. 683-686.

[12]. David Rennie, Manoj Sachdev, “A Novel Tri-State Binary Phase Detector”. ISCAS 2007 IEEE International Symposium on Digital Object Identifier, pp. 185-188.

[13]. John Carr, and Brian Frank, (2009). “Static Phase Offset in a Multiplying Phase Detector”. IEEE Microwave & Wireless Components Letters, Vol. 19, No. 8, pp. 518-520.

[14]. M. Soyuer and R. G. Meyer, (1989). “High-frequency phase-locked loops in monolithic bipolar technology”. IEEE J. Solid-State Circuits, Vol. 24, No. 3, pp. 787–795.

[15]. M. Madihian, (1993). “A Wide Dynamic-Range Phase Detector for Advanced Communication Systems Application”. IEEE, Communications, Computers and Power in the Modern Environment, Conference, pp. 192-195.

i-manager's Journal on Circuits and Systems (JCIR)

Current Issue Vol. 11 Issue 2

Most Read

Most Cited

Volume 4 Issue 1 December - February 2016 [Open Access]

Multricor [“Multiple Trichotomous Correlation”Analysis]: The Post Hoc Examination and Measurement of Statistically Significant Tri–Squared Tests to Determine the Total and Internal Strength of Relationships between Trichotomous Variables Used For Dynamic Psychometric Circuit Assessment

James Edward Osler II*

Faculty Member, Department of Curriculum and Instruction, North Carolina Central University (NCCU) School of Education, USA.

Abstract

References

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Design of Wideband Sub-Harmonic Receiver Front-End Using 0.18µm CMOS Technology

K. Rajesh* , K. Neelima**

* PG Scholar, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College, Rangampet, Tirupati, India. ** Assistant Professor, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College, Rangampet, Tirupati, India.

Rajesh, K., and Neelima, K. (2016). Design of Wideband Sub-Harmonic Receiver Front-End Using 0.18µm CMOS Technology. i-manager’s Journal on Circuits and Systems, 4(1), 12-15. https://doi.org/10.26634/jcir.4.1.6030

Abstract

References

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Efficient Realization of Reversible Gray to Binary Code Converter Circuit

Gowthami P.*

Research Scholar, Department of Electronics and Communication Engineering, S V University College of Engineering, Tirupati, Andhra Pradesh, India.

Gowthami P. (2016). Efficient Realization of Reversible Gray to Binary Code Converter Circuit. i-manager’s Journal on Circuits and Systems, 4(1), 16-19. https://doi.org/10.26634/jcir.4.1.6031

Abstract

References

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Power Gating Techniques for Leakage Reduction in CMOS Circuits - A Brief Survey

M. Kavitha* , T. Govindaraj**

* Assistant Professor, Department of Electronics and Communication Engineering, Government College of Engineering, Bargur, India. ** Professor, Department of Electrical and Electronics Engineering, VSB Engineering College, Karur, India.

Kavitha, M. and Govindaraj, T. (2016). Power Gating Techniques for Leakage Reduction in CMOS Circuits - A Brief Survey. i-manager’s Journal on Circuits and Systems, 4(1), 20-26. https://doi.org/10.26634/jcir.4.1.6032

Abstract

References

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OTRA Based Phase Detector Design

Mamatha Malisetty* , C. V. Sudhakar**

* PG Scholar, Department of VLSI, Sree Vidyanikethan Engineering College, Tirupathi, India. ** Assistant Professor, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College, Tirupathi, India.

Mamatha, M. and Sudhakar, C.V. (2016). OTRA Based Phase Detector Design. i-manager’s Journal on Circuits and Systems, 4(1), 27-33. https://doi.org/10.26634/jcir.4.1.6033

Abstract

References

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* PG Scholar, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College, Rangampet, Tirupati, India.

** Assistant Professor, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College, Rangampet, Tirupati, India.

* Assistant Professor, Department of Electronics and Communication Engineering, Government College of Engineering, Bargur, India.

** Professor, Department of Electrical and Electronics Engineering, VSB Engineering College, Karur, India.

* PG Scholar, Department of VLSI, Sree Vidyanikethan Engineering College, Tirupathi, India.

** Assistant Professor, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College, Tirupathi, India.