Design Of a Novel Gated 5T SRAM Cell with Low Power Dissipation in Active and Sleep Mode

K. Neelima*, K. C. Lakshmi Narayana**
* M.Tech Student, Department of ECE, Siddartha Educational Academy Group of Institutions, Chinthagunta (V), Near C.Gollapalli, Tirupati.
** Assistant Professor, Department of ECE,Siddartha Educational Academy Group of Institutions, Chinthagunta (V), Near C.Gollapall , Tirupati.
Periodicity:September - November'2014


As technology scales down, the leakage power becomes dominant due to the second order effects of the transistors. The leakage power aids in considerable increase of the total power dissipation of the device. The existing SRAM cells at submicron region dissipate more power and become in stable in spite of applying low power techniques like multithreshold logic, body biasing techniques, stacked structures etc. This paper concentrates on low power highly stable SRAM cell using only five transistors and a low power technique called Gated Bias Technique. In this paper, the schematics are developed using Digital Schematic Tool and the corresponding layouts are developed using Microwind Tool. The designs are optimized for low area with good stability and low power dissipation. Further they are compared for various Technologies downline from 180nm to 90nm.


SRAM, Gated Bias Technique, Body Biasing Technique, Submicron Region.

How to Cite this Article?

Neelima, K., and Narayana, K. C. L. (2014). Design Of a Novel Gated 5T SRAM Cell with Low Power Dissipation in Active and Sleep Mode. i-manager’s Journal on Circuits and Systems, 2(4), 13-20.


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