Leakage Power Reduction Using Multi Modal Driven Hierarchical Power Mode Switches

M. Chandra Sekhar Reddy*, P. Ramana Reddy **
*Research Scholar, Department of Electronics and Communication Engineering, JNTUACEA, Anantapuramu, Andhra Pradesh, India.
** Professor, Department of Electronics and Communication Engineering, JNTUACEA, Anantapuramu, Andhra Pradesh, India..
Periodicity:March - May'2018
DOI : https://doi.org/10.26634/jcir.6.2.14291

Abstract

This article presents a scalable power-gating scheme approach to reduce leakage power using intermediate poweroff modes. An important limitation in power-gating scheme is its variations with wakeup time during activation mode changes, as is often the case. The authors have proposed a novel power-gating scheme that are accomplished by hierarchical mode activation to reduce worst case delay bound. The system combines the advantages of leakage power reduction and wake up time optimization. The influence of power-gating scheme on circuit performance is studied and concluded that finite power-off modes, scalable modes are important for good performance. Key selection of power-off modes over entire circuit is complex and it is computationally more expensive. To get more accurate modes with finite trade off in wake up time, this new approach gives near-perfect ways of isolating modes from other changes. The complete power-gating scheme system was evaluated on a multiplier logic core as a test sample and also compared against well known power-gating schemes.

Keywords

Leakage Reduction, Multi threshold Complementary Metal Oxide Semiconductor (MTCMOS), Static Power, Ground Bounce.

How to Cite this Article?

Reddy, M. C. S., and Reddy, P. R. (2018). Leakage Power Reduction Using Multi Modal Driven Hierarchical Power Mode Switches. i-manager’s Journal on Circuits and Systems, 6(2), 1-7 https://doi.org/10.26634/jcir.6.2.14291

References

[1]. Anis, M., Mahmoud, M., Elmasry, M., & Areibi, S. (2002). Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique. In Proceedings of the 39th Annual Design Automation Conference (pp. 480-485). ACM.
[2]. Chowdhury, M. H., Gjanci, J., & Khaled, P. (2008). Innovative power gating for leakage reduction. In Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on (pp. 1568-1571). IEEE.
[3]. Gonzalez, R., Gordon, B. M., & Horowitz, M. A. (1997). Supply and threshold voltage scaling for low power CMOS. IEEE Journal of Solid-State Circuits, 32(8), 1210- 1216.
[4]. Heydari, P., & Pedram, M. (2003). Ground bounce in digital VLSI circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 11(2), 180-193.
[5]. Hu, J., Zhou, D., & Wang, L. (2007). Power-gating adiabatic flip-flops and sequential logic circuits. In Communications, Circuits and Systems, 2007. ICCCAS 2007. International Conference on (pp. 1016-1020). IEEE.
[6]. Kim, K. K., Nan, H., & Choi, K. (2009). Ultra low-voltage power gating structure using low threshold voltage. IEEE Transactions on Circuits and Systems II: Express Briefs, 56(12), 926-930.
[7]. Kim, N. S., Austin, T., Baauw, D., Mudge, T., Flautner, K., Hu, J. S., ... & Narayanan, V. (2003). Leakage current: Moore's law meets static power. Computer, 36(12), 68-75.
[8]. Lackey, D. E., Zuchowski, P. S., Bednar, T. R., Stout, D. W., Gould, S. W., & Cohn, J. M. (2002). Managing power and performance for system-on-chip designs using voltage islands. In Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design (pp. 195-202). ACM.
[9]. Min, K. S., Choi, H. D., Choi, H. Y., Kawaguchi, H., & Sakurai, T. (2006). Leakage-suppressed clock-gating circuit with zigzag super cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-V/Sub DD/LSIs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(4), 430-435.
[10]. Nguyen, D., Davare, A., Orshansky, M., Chinnery, D., Thompson, B., & Keutzer, K. (2003). Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization. In Proceedings of the 2003 International Symposium on Low Power Electronics and Design (pp. 158-163). ACM.
[11]. Pant, P., De, V. K., & Chatterjee, A. (1998). Simultaneous power supply, threshold voltage, and transistor size optimization for low-power operation of CMOS circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, (4), 538-545.
[12]. Pant, P., Roy, R. K., & Chatterjee, A. (1999). Dualthreshold voltage assignment with transistor sizing for low power CMOS circuits. In Circuits and Systems, 1999. 42nd Midwest Symposium on (Vol. 1, pp. 26-29). IEEE.
[13]. Singh, R., Kim, A., Kim, S., & Kim, S. (2010). A threestep power-gating turn-on technique for controlling  ground bounce noise. In Proceedings of the 16th ACM/IEEE International Symposium on Low Power Electronics and Design (pp. 171-176). ACM.
[14]. Veendrick, H. J. (1984). Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits. IEEE Journal of Solid-State Circuits, 19(4), 468-473
[15]. Wang, Q., & Vrudhula, S. B. (1998). Static power optimization of deep submicron CMOS circuits for dual Vt technology. In Proceedings of the 1998 IEEE/ACM International Conference on Computer-aided Design (pp. 490-496). ACM.
[16]. Wei, L., Chen, Z., Roy, K., Johnson, M. C., Ye, Y., & De, V. K. (1999). Design and optimization of dual-threshold circuits for low-voltage low-power applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 7(1), 16-24.
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