Low Power Optimization Technique Based Linear Feedback Shift Register

Dharmendra Singh*, Ankit Singh**, Prachi Agrawal***, Harshita Agrawal****
*-** Assistant Professor, Department of Electronics and Telecommunication Engineering, SSIPMT, Raipur, India.
***-**** UG Scholar, Department of Electronics and Telecommunication Engineering, SSIPMT, Raipur, India.
Periodicity:December - February'2018
DOI : https://doi.org/10.26634/jcir.6.1.14058


In Very-Large-Scale Integration (VLSI), the main challenges for the researchers are to reduce the power dissipation by the devices. In this paper, the authors have proposed a modified version of the Linear Feedback Shift Register to meet the specific output. The power consumption can be reduced by deactivating the clock signal from the flip flop to design test pattern generator during testing power. The LFSR pseudo-random test pattern generator is used in the testing of the ASIC chips, which is used to generate the random sequences of the desired pattern generator. This paper will help in the reduction of additional test inputs used for the ASIC. The test pattern is generated in such a way that the component requirements can be reduced.


Linear Feedback Shift Register (LFSR), Low Power, Optimization, Built-In Self-Test (BIST), Test Patterns.

How to Cite this Article?

Singh, D., Singh, A., Agrawal, P., and Agrawal, H. (2018). Low Power Optimization Technique Based Linear Feedback Shift Register. i-manager’s Journal on Circuits and Systems, 6(1), 20-24. https://doi.org/10.26634/jcir.6.1.14058


[1]. Ahmed, N., Tehranipour, M. H., & Nourani, M. (2004). Low power pattern generation for BIST architecture. In Circuits and Systems, 2004. ISCAS'04. Proceedings of the 2004 International Symposium on (Vol. 2, pp. II-689-92). IEEE.
[2]. Ajane, A., Furth, P. M., Johnson, E. E., & Subramanyam, R. L. (2011). Comparison of binary and LFSR counters and efficient LFSR decoding algorithm. In Circuits and Systems th (MWSCAS), 2011 IEEE 54 International Midwest Symposium on (pp. 1-4). IEEE.
[3]. Brock, T. B. (2006). Linear Feedback Shift Registers in SAGE, 1-18.
[4]. Gunavathi, K., Paramasivam, K., Lavanya, P. S., & Umamageswaran, M. (2006). A novel BIST TPG for testing of VLSI circuits. In Industrial and Information Systems, First International Conference on (pp. 109-114). IEEE.
[5]. Haridas, N., & Devi, M. N. (2011). Modified Genetic Algorithm for Deciding LFSR Configuration, 2(2), 34-36.
[6]. Kaur, R., & Baja, N. (2012). Enhancement in Feedback Polynomials of LFSR used in A5/1 Stream Cipher. International Journal of Computer Applications, 57(19), 32-35.
[7]. Muttoo, S. K., & Abdulsattar, I. (2012). A new stegosystem based on LFSR generator. International Journal of Engineering and Innovative Technology (IJEIT), 1(1), 40-43.
[8]. Prasada Rao, R. V., Varaprasad, N. A., Babu, G. S., & Mohan, C. M. (2013). Power Optimization of Linear Feedback Shift Register (LFSR) for Low Power BIST implemented in HDL. International Journal of Modern Engineering Research (IJMER), 3(3), 1523-1528.
[9]. Tehranipoor, M., Nourani, M., & Ahmed, N. (2005). Low transition LFSR for BIST-based applications. In Test th Symposium, 2005. Proceedings. 14 Asian (pp. 138-143). IEEE.
[10]. Zeng, G., Han, W., & He, K. (2007). High Efficiency Feedback Shift Register: Sigma-LFSR. IACR Cryptology ePrint Archive, 2007, 114.
If you have access to this article please login to view the article or kindly login to purchase the article

Purchase Instant Access

Single Article

North Americas,UK,
Middle East,Europe
India Rest of world
Pdf 35 35 200 20
Online 35 35 200 15
Pdf & Online 35 35 400 25

Options for accessing this content:
  • If you would like institutional access to this content, please recommend the title to your librarian.
    Library Recommendation Form
  • If you already have i-manager's user account: Login above and proceed to purchase the article.
  • New Users: Please register, then proceed to purchase the article.