Dual Frequency Circular Shaped Two Port MIMO Antenna
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Computer Modeling and Simulation of Ultrasonic Signal Processing and Measurements
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Dual Frequency Circular Shaped Two Port MIMO Antenna
This paper gives information about the comparison of adaptive filtering techniques like fixed LMS, Normalized Least Mean Square, and RLS for noise elimination in speech communication systems. The main objective of this paper is to suppress the additive noise which is due to the effect of environmental conditions in the communication systems. In these days, additive noise is one of the major problems in the communication, especially in the digital electronic circuit design. The origins of additive noise are because of atmospheric conditions, weather situations around the system and any other disturbances. Generally, the coefficients of filter updation in a basic filter does not occur time to time, as it may affect the desired information. By updating the coefficients of the filter time to time, this problem could be eradicated and thereby increasing the number of iterations for the filtering process, which gives efficient results. In the communication systems, the performance of these adaptive filters are in terms of mean square error, signal to noise ratio, rate of convergence, etc. In this research paper, the authors have discussed about how to cancel out the additive noise which is combined to the input speech signals that observes the records of signal to noise ratio, and mean square error. Finally, this article compares those results experimentally with the help of MATLAB programming and calculation tool. The mean square error improvement with the number of iterations for different noise signals are represented graphically. By the observation of the graphical results, the rate of convergence and reception level for the given speech and noise signals were found.
This paper is devoted to design a high-speed Arithmetic Logic Unit. All of us know that, ALU is a module which can perform arithmetic and logic operations. The speed of ALU greatly depends upon the speed of the Multiplier. This paper presents a technique called, “Vedic Mathematics” for designing the multiplier that is fast as compared to other multipliers based on mathematical techniques that have been in practice for a long time. Here, a high-speed 32x32 bit multiplier is designed and analyzed which is based on the Vedic mathematics mechanism. The proposed method is efficient and fast, wherein the processing involves the vertical and crossed multiplication of precedent Vedic mathematics. The internal multiplier is implemented using Vedic-Wallace structure for high-speed implementation. The exponent of the final result is obtained by using Brent-Kung adder for fast computations with less area utilization. The projected Vedic multiplier is coded in a High-level Digital Language (VHDL) followed by synthesization using an EDA tool, XilinxISE14.5. The proposed ALU is able to perform three different arithmetic and eight different logical operations at high speed. The main objective of this paper is to increase the speed of the multiplier and to decrease the delay, and area of the hardware.
In this paper, a compact wideband Band pass filter has been designed. Quadruple resonance modes are generated by using the inter digital coupled lines and multimode resonator to achieve a wideband. By adding stubs with multimode ring resonator, an extra transmission poles is introduced at 3.5GHz. By introduction of transmission zero at 5.8 Ghz, a good stop band performance is achieved. Designed Bandpass filter is well suited for WLAN at 2.45 and 5.2 GHz. A wide pass band is achieved from 2.45 GHz to 5.2 GHz providing 3 dB Bandwidth of 2.75 GHz and 3 dB Fractional Bandwidth of 71.8%. Good insertion loss nearly about 1.7 dB and return loss more than 15 dB are achieved with high selectivity at both sides of pass band. Designed filter is simulated using the commercially available simulation tool, HFSS.
Digital multipliers are widely used in the arithmetic units of microprocessors, multimedia and digital signal processors. The main aim of this research work is to design high performance multipliers using different radix to different adders. Modified booth encoding technique is used in this proposed design, where extra partial products are reduced to half. Therefore, the accumulation stages are reduced. By this design, it significantly improves speed, area and delay which is a main objective and purpose of the study. Modified booth encoding technique improves the power delay product by using different types of adders with different radix such as radix-4, radix-8, and radix-16. The used adders are ripple carry adder and carry look-ahead adder, where these are used to know the exact difference by their comparison in terms of delay and area by using Xilinx ISE 14.5 tool with high performance parameters.
In this paper, a Dual Loop PLL has been designed. In the proposed design, a DL-PLL is designed in two ways. The first method is, that the two PLLs are connected to a mixer and in the second method, the two PLLs are directly cascaded. The two designs will give better results, when compared with the normal CP-PLL. The proposed DL-PLL consists of an AND based PFD and a CP circuit with switching scheme, such that the proposed PFD eliminates the missing edge and phase ambiguity problems in the conventional PFDs circuit. Also, a novel CP circuit with a special switching scheme has been incorporated to reduce the current mismatch error and the charge injection error problem with this new design technique. By using the normal CP-PLL, the total noise performance will be -91.134 dB/Hz and the power dissipation will be 357831.4 mW. By using the DL-PLL with a mixer, the power dissipation will be reduced to 4.2005 mW, but the total noise performance will be somewhat good. By using the second type of DL-PLL that is by directly cascading two PLLs, the power dissipation is reduced to 2.581 mW and the total noise performance will be -133.93 dBc/Hz at 100 MHz offset frequency for a load capacitance of 0.01 μF. The current noise of the PFD and CP circuit has been measured from the transistor level simulation to find the phase noise of the Dual Loop PLL, for output frequency of 2.4 GHz with 100 MHz reference signal in Hspice (Hspui) using awan waves and HSPICE RF Tool. The proposed Dual Loop PLL will have an improved noise performance of -42 dB when compared to the existing charge pump PLL circuits. In addition, the total noise and power dissipation modeling has been done to find the output total noise and Power dissipation of the PLL, considering the PFD and CP output current noise measured at the transistor level in 0.18 μm CMOS.
An embedded active inductance technique is used in 2.41GHz ISM Receiver IQ VCO-mixer. The receiver consists of an active inductance topology and the VCO-mixer network, which is designed for low area and low power. The VCO-mixer is based on an IQ cross-coupled embedded active inductor VCO, where the two single oscillators are coupled through active loads. RC oscillators have the advantage of being inductorless (i.e. low area), while typically having a high power consumption. As for quadrature, the coupling of two single oscillators is done with a shunt technique that uses PMOS as active loads, instead of the resistors. The mixer is an add-on to this oscillator, taking advantage of its similarities with a single-balanced mixer. The use of the active load increases the conversion gain. This topology consumes approximately 11.4 % less power in comparison to the IQ cross-coupled RC relaxation VCO-mixer. The mixing function is incorporated in the IQ VCO, benefiting from an increased gain. The receiver IQ VCO-mixer has a gain of 12.22 dB and a noise figure of 7.98 dB, consuming 7.98 mW from a 1.2 V power supply.
