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i-manager's Journal on Electronics Engineering (JELE)

Current Issue Vol. 15 Issue 1

Most Cited

Volume 5 Issue 3 March - May 2015

Research Paper

Design of FIR Filter for Efficient FPGA Implementation

S. V. Padmajarani* , 0**

* Professor and HOD, Department of Electronics and Communication Engineering, Sree Venkateswara College of Engineering, A.P, India.

** Principal, Sree Venkateswara College of Engineering and Technology, Chittoor, A.P, India.

Padmajarani, S.V. , and Muralidhar, M. (2015). Design Of FIR Filter For Efficient FPGA Implementation. i-manager's Journal on Electronics Engineering, 5(3), 1-10. https://doi.org/10.26634/jele.5.3.3392

Abstract

FIR filters are basic building blocks in Digital Signal Processing applications, require computationally efficient multiply and accumulate operations so the blocks with the desired characteristics have to be chosen carefully. The multiplier is generally slow and occupies large area, the adder also contributes to long delay when the length of the addition is more. Improving the speed results mostly in large areas, usually they conflict with each other. The signal processing applications consume considerable amount of energy. Hence there is a need for low power, high speed, low area circuits for Digital Signal Processing applications. The aim of this paper is to implement a low power, high speed, area efficient FIR filter. Multiply and Accumulate technique is used for multiplier design and the addition and accumulation operations are performed by Parallel Prefix Adders. Some of the available Parallel Prefix Adder architectures and the hybrid architecture of Parallel prefix adder is used here. The implementation is done for 4-tap FIR filter using Xilinx 14.5 version, with the targeted device of Spartan3E FPGA. The experimental results show that the implemented FIR filter using hybrid parallel prefix adder is efficient in area, consume low power and has high speed compared to existing parallel prefix adder models.

References

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[7]. Cui Guo-wei., & Wang Feng-ying. (2013). “The Implementation of FIR Low-pass Filter Based on FPGA and DA”. IEEE International Conference on Intelligent Control and Information Processing(ICICIP).

[8]. Dawoud, D.S., & Masupa, S. (2006). “Design and FPGA Implementation of Digit-Serial FIR Filters”, South African Institute of Electrical Engineers, AFRICON, Vol. 97, No. 3, pp. 216-221.

[9].Deepak G., P.K.Meher.,& A.Sluzek. (2007). “Performance Characteristics of Parallel and Pipelined Implementation of FIR Filters in FPGA Platform”. IEEE International Symposium on Signals, Circuits and Systems (ISSCS) 2007.

[10]. Dong Shi.,& Ya Jun Yu. (2011). “Design of Linear Phase FIR Filters with High Probability of Achieving Minimum Number of Adders”, IEEE Trans. Circuits and Systems, Vol.58, No. 1, pp. 126-136.

[11]. Dr. Hikmat.,& Abdullah, N. (2008). “Design and Implementation of Programmable FIR filter using FPGA”, Eng.& Tech, Vol. 26, No. 7.

[12]. Fabian Daitx., F.,Rosa,V.S., Eduardo Costa., Paulo Flores.,& Bampi, S. (2008). “VHDL Generation of Optimized FIR Filters”. IEEE International Conference on Signals, Circuits and Systems.

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[21]. LeventAksoy., Cristiano Lazzari.,Eduardo Costa., Paulo Flores.,& Jose Monteriro. (2013). “Design of Digit- Serial FIR Filters: Algorithms, Architectures, and a CAD Tool”. IEEE Trans. VLSI Systems, Vol. 21, No. 3, pp. 498-511.

[22]. LeventAksoy., Eduardo Costa., Paulo Flores.,& Jose Monteiro. “Minimum Number of Operations under a General Number Representation for Digital Filter Synthesis”.

[23]. Mahesh Kadam., Kishore Sawarkar.,& Sudhakar Mande. (2015). “Investigation of suitable DSP Architecture Efficient FPGA Implementation of FIR Filter ”. IEEE International Conference on Communication, Information & Computing Technology (ICCICT).

[24]. Mohmed al mahdiEshawie., & Masurie Bin Othman. (2008). “An Algorithm Proposed for FIR Filter Coefficient Representation”. International Journal of Mathematics and Computer Sciences. pp. 24-30.

[25]. Narendra Singh Pal., Harjit Pal Singh.,R.K.Sarin., & Sarabjeet Singh (2011). “Implementation of High Speed Fir Filter using Serial and Parallel Distributed Arithmetic Algorithm”, IJCA, Vol. 25, No. 7, pp. 26-32.

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[27]. Padmajarani, S.V., & Muralidhar, M. (2011). “A Hybrid Parallel Prefix Adder for high speed computing”. Proc. 7th National Conference on Advances in Electronics and Communications(ADELCO).

[28]. Padmajarani, S.V., & Muralidhar, M. (2012). “Design and Implementation of a Hybrid High Speed Area Efficient Parallel Prefix Adder in an FPGA”. International Journal of Computer Applications (IJCA), Vol. 58, No. 1, pp. 17-21.

[29]. Padmajarani, S.V., & Muralidhar, M. (2012). “A New Approach to implement Parallel Prefix Adders in an FPGA”. International Journal of Engineering Research and Applications (IJERA), Vol. 2, No. 4, pp.1524-1528.

[30]. Padmajarani, S.V., & Muralidhar, M. (2012). “Comparison of Parallel Prefix Adders Performance in an FPGA”. International Journal of Engineering Research and Development (IJERD), Vol. 3, No. 6, pp. 62-67.

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[32]. Pramod Kumar Meher. (2010). “New Approach to Look-Up-Table Design and Memory-Based Realization of FIR Digital Filter”. IEEE Trans. Circuits and Systems, Vol. 57, No.3, pp. 592-603.

[33]. Pramod Kumar Meher., Shruti saga Chandrasekharan., & Abbes Amira. “FPGA Realization of FIR Filters by Efficient and Flexible Systolization Using Distributed Arithmetic”. IEEE Trans. Signal Processing, pp.1- 9.

[34]. Raja, L.,Prabhu, B.M., & Thanushkodi, K. (2011). “Design of Low power Digital Multiplier using Dual Threshold Voltage Adder Module”. Elsevier, International Conference on Communication Technology and System Design.

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[36]. RavinderKaur., AshishRaman.,Hardev Singh.,& JagjitMalhotra. (2011). “Design and Implementation of High Speed IIR and IIR Filter using Pipelining”. IJCETE, Vol. 3, No. 2, pp. 292-295.

[37]. Raymon.,& Andraka, J. “FIR Filters Fits in an FPGA using a Bit Serial Approach”, pp. 1-8.

[38]. SabastienBilavarn, Guy Gogniat, Jean-Luc Philippe, & Lilian Bossuet. (2006). “Design Space running Through Early Estimations of Area/Delay Tradeoffs for FPGA Implementations”. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, No. 10, pp. 1950- 1968.

[39]. SaeeidTahmasbiOskuii. “Design of Low power reduction Trees in parallel Multipliers”. (Doctoral dissertation). Norwegian University of Science and Technology, Trondheim, Norway.

[40]. SanjitK.Mitra. (2013). “Digital Signal Processing, A th Computer-Based Approach”, (4 edition), Mc.Graw Hill Education.

[41]. SatishMohanakrishnan & Joseph B. Evans. “A Frame for the Design of High Sped FIR Filters on FPGAs”. Telecommunications & Information Sciences Laboratory, University of Kanas, Lawrence, KS 66045-2228.

[ 42].ShahnamMirzaei., Ryan Kastner.,& Anup Hosangadi. (2010). “Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs”. International Journal of Reconfigurable Computing, Vol. 2010, pp.1-17.

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[44]. TaekoMatsunaga, Shinji Kimura,& Yusuka Matsunaga. (2008). “Synthesis of parallel prefix adders considering switching activities”. IEEE International Conference on computer design, pp. 404-409.

[45]. TaekoMatsunaga.,& YusukaMatsunaga. (2007). “Timing-Constrained Area minimization Algorithm for parallel prefix adders”. IEICE TRANS, Fundamentals,E90- A(12).

[46]. Yajun Zhou., & Pingzheng Shi. (2011). “Distributed Arithmetic for FIR Filter implementation on FPGA”. IEEE International Conference on Multimedia Technology (ICMT).

[47]. Yamada. M., & Nishihara. A. (2001). “High Speed FIR Digital Filter with CSD Coefficients Implemented on FPGA”. Proc. IEEE Design and Automation Conference, 7-8.

[48]. Yu-Chi Tsa.,& Ken Choi. (2012). “Area- Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithms”. IEEE Trans. Circuits and Systems, Vol. 59, No. 6, pp. 371-375.

[49]. Zhangwen Tang., Jie Zhang., & Hao Min. (2002). “A High-speed, Programmable, CSD Coefficient FIR Filter”. IEEE Trans. Consumer Electronics, Vol. 48, No. 4, pp. 834- 837.

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Research Paper

An Efficient Architecture For Single Precision Floating Point Multiplier Using Various Algorithms

K. Charan Kumar* , Sunil Kumar K**

* Assistant Professor, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College (Autonomous), Tirupati.

** B.E Student, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College (Autonomous), Tirupati.

Kumar, K.C., and Kumar, K.S., (2015). An Efficient Architecture For Single Precision Floating Point Multiplier Using Various Algorithms. i-manager's Journal on Electronics Engineering, 5(3), 11-21. https://doi.org/10.26634/jele.5.3.3393

Abstract

This paper presents the design and comparison of the high speed single precision binary floating point multiplier using IEEE-754 format implemented through the Faster Dadda, Vedic from Dadda and the modified Booth algorithm. The Faster Dadda algorithm utilizes the parallel independent column compression technique and the Hybrid adder. The Vedic from Dadda is the concept of utilizing the Dadda to get higher order multiplier through Vedic concept. Integer multiplication can be inefficient and costly, in time and hardware, depending on the representation of signed numbers. The modified Booth algorithm uses the encoding techniques which minimize the partial products. These single precision Floating point multipliers based on IEEE 754 are implemented using VHDL and they are targeted for Xilinx Spartan-3E FPGA. The performances of these multipliers are analysed in terms of speed, area and area-delay product.

References

[1]. The Institute of Electrical and Electronic Engineers Inc., (1985).“IEEE standard for Binary-floating Point Arithmetic”, ANSI/IEEE Std 754-1985.

[2]. Mike Field (2012). “Introducing the Spartan 3E FPGA and VHDL”, an ebook, pp. 12-18.

[3]. C. S. Wallace, (1964). “A Suggestion for a Fast Multiplier”, IEEE trans. on computers, Vol. 13, pp. 14 -17.

[4]. L. Dadda, (1965). “Some schemes for parallel Multipliers”, Alta Frequenza, Vol. 34, pp. 349-356.

[5]. Whitney J. Townsend, J. A. Abraham and Earl E. Swartzlander, (2003). “A Comparison of Dadda and Wallace multiplier delays”, Computer Engineering Research Centre, Proc. SPIE, Advanced Signal Processing Algorithms, Architectures and Implementations XIII, pp. 552-560.

[6]. AniruddhaKanhe, Shishir Kumar Das, Ankit Kumar Singh, (2012). “Design and Implementation of Floating Point Multiplier based on Vedic Multiplication Technique”, International Conference on Communication, Information & Computing Technology (ICCICT).

[7]. B. Ramkumar, V. Sreedeep and Harish M Kittur, member IEEE. “A Design Technique for Faster Dadda Multiplier”, Integrated Circuits Design Laboratories, VIT University.

[8]. Poornima M, Shivaraj Kumar Patil, Shivukumar , Shridhar K P , Sanjay H, (2013). “Implementation of Multiplier using Vedic Algorithm”, International Journal of Innovative Technology and Exploring Engineering (IJITEE) ISSN: 2278-3075, Vol. 2, No. 6.

[9]. SandeepShrivastava, Jaikaran Singh, MukeshTiwari, (2011). “Implementation of Radix-2 Booth Multiplier and Comparison with Radix-4 Encoder Booth Multiplier”, International Journal on Emerging Technologies, ISSN: 0975-8364, Vol. 2, No. 1.

[10]. S. Shrivastava, P. Gulhane, (2014). “Optimized model of Radix-4 Booth Multiplier in VHDL”, International Journal of Emerging Technology and Advanced Engineering (IJETAE), ISSN 2250-2459, Vol. 4.

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Research Paper

An Efficient Design Of XOR Gate And Its Applications Using QCA

D. Ajitha* , K. V. Ramanaiah, V. Sumalatha*

* Assistant Professor, Department of Electronics and Communication Engineering, SITAMS, Chittoor

Associate Professor & HOD, Department of Electronics and Communication Engineering, YSR Engineering College, Proddatur.

* Professor, Department of Electronics and Communication Engineering, JNTUA College of Engineering, Ananthapuramu

Ajitha , D., Ramanaiah, K.V., and Sumalatha, V. (2015). An Efficient Design Of XOR Gate And Its Applications Using QCA. i-manager's Journal on Electronics Engineering, 5(3), 22-29. https://doi.org/10.26634/jele.5.3.3394

Abstract

As a substitute for CMOS, innovation of quantum cellular automata was anticipated by Lent et al, to represent exemplary cell automata with quantum dots. Quantum Cellular Automata (QCA) may be a progressive innovation that endeavors the certain nano level issues to perform computing. Its potential advantages are high speed, high device density, and low power dissipation. This paper presents the design of XOR gate with the least number of cells; furthermore the circuit appearance is simple. Exploitation of this novel XOR gate leads to the development of combinational circuits like Half Adder, Full Adder, Parity Generator and Parity Checker etc., which were developed effectively in a single layer structure with less number of cells, area and delay, as compared to the earlier designs. This paper mainly focusses on the construction of optimized combinational circuits without using cross-overs in QCA. Further, the simulation results are presented.

References

[1]. Y. Taur, (2002). “CMOS design near the limit of scaling”, IBM J. Res. & Dev. Vol. 46, No. 2/3

[2]. Shekhar Borkar, (1999). “Design Challenges Of Technology Scaling”,Micro IEEE, Vol. 9, pp. 23-29.

[3]. P. Douglas Tougaw & Craig S. Lent, (1994). “Logical devices implemented using Quantum Cellular Automata” Automata, J. Appl. Phys. Vol. 75, No. 3.

[4]. K. Kim, K. Wu, R. Karri, (2005). “Towards designing robust QCA architectures”, Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, pp. 1214–1219.

[5]. Prameela KumariN, K. S.Gurumurthy, (2014). “Quantum Dot Cellular Automata: A Review”, Proc. of the Int.Conf. on Advances in Computing and Information Technology- ACIT, pp. 51-55.

[6]. Rumi Zhang ,KonradWalus, WeiWang,, & Graham A. Jullien, (2004). “A Method of Majority Logic Reduction for Quantum Cellular Automata”, IEEE Transactions on Nanotechnology, Vol. 3, No. 4, pp. 443-450.

[7]. J. Iqbal, F. A. Khanday, N. A. Shah, (2013). Design of Quantum-dot Cellular Automata (QCA) based modular 2n-1-2n MUX-DEMUX, proceedings of IMPACT, pp. 189- 193.

[8]. M. Mustafa, M R Beigh, (2013). “Design and implementation of Quantum Cell Automata based novel parity generator and checker circuits with minimum complexity and cell count”, Indian Journal of pure & applied physics, Vol.51, pp. 60-66.

[9]. Mohammad Rafiq Beigh, Mohammad Mustafa, Firdous Ahmad, (2013). Performance Evaluation of Efficient XOR Structures in Quantum-Dot Cellular Automata (QCA), Circuits and Systems, Vol. 4, pp. 147- 156.

[10]. Santanu Santra, Utpal Roy, (2014). “Design and Implementation of Quantum Cellular Automata Based Novel Adder Circuits”, World Academy of Science, Engineering and Technology ,International Journal of Computer, Information, Systems and Control Engineering, Vol, 8, No.1.

[11]. Mariam Momenzadeh, Jing Huang, Mehdi B.Tahoori & Fabrizio Lombardi, (2005). “Characterization, Test, and Logic Synthesis of And-Or-Inverter (AOI) Gate Design for QCA Implementation”, in IEEE Transactions On Computer-Aided Design Of Integrated Circuits And Systems, Vol. 24, No. 12, pp. 1881-1893.

[12]. Heumpil Cho, (2006). “Adder and Multiplier Design and Analysis in Quantum-dot Cellular Automata”, PhD dissertation, University of Texas At Austin.

[13]. Firdous Ahmad, Ghulam Mohiuddin Bhat, Peer Zahoor Ahmad, (2014). “Novel Adder Circuits Based On Quantum-Dot Cellular Automata (QCA)”, Circuits and Systems, Vol. 5, pp.142-152.

[14]. Weiqiang Liu,Liang Lu, M´aire O'Neill, & Earl E. Swartzlander.Jr, (2013), “A First Step Towards Cost Functions for Quantum-dot Cellular Automata Designs”,IEEE Transactions on Nanotechnology, pp.1-13.

[15]. Konrad Walus, Timothy J. Dysart, Graham A. Jullien & R. Arief Budiman, (2004). “QCA Designer: A Rapid Design and Simulation Tool for Quantum-Dot Cellular Automata”, IEEE Transactions On Nanotechnology, Vol. 3,No.1, pp. 26-31.

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Research Paper

A Novel Pliant Nanogenerator Made Of PDMS and ZnO Nanoparticles

Mareddi Bharathkumar* , Palagani Yellappa, D. Revanth*

*-*** M.Tech Student, VLSI, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College, Tirupathi.

Bharathkumar, M., Yellappa, P., and Revanth, D. (2015). A Novel Pliant Nanogenerator Made Of PDMS and ZnO Nanoparticles. i-manager's Journal on Electronics Engineering, 5(3), 30-34. https://doi.org/10.26634/jele.5.3.3395

Abstract

In this paper, a novel pliant nanogenerator made of PDMS (polydimethylsiloxane) and ZnO nanoparticles is presented. In this device, ZnO nanoparticles are combined with PDMS to form a nanogenerator. PDMS is a flexible kind of material, which is used to form flexible kind of materials and ZnO is a piezoelectric material which exhibits piezoelectricity. A nanogenerator converts mechanical energy into electrical energy. Mechanical energy refers to energy that we are getting from the surroundings like mechanical pressure, mechanical vibrations, etc. By using this energy we can charge batteries of mobile phones and operate smaller electronic devices through wireless power transmission and also it can give endless power in wireless sensor applications. Now a days people are mainly facing problems with power and low battery power. So, to avoid these problems, energy harvesting is playing a main role in industries. Our work indicates the realization of plaint nanogenerator made of ZnO nanoparticles and PDMS and it has some important and interesting applications in energy harvesting. The applications are mainly for low power electronic devices.

References

[1]. Hui Sun, He Tian, Yi Yan, Dan Xie, Yu-Chi Zhang, Xuan Liu, Shuo Ma, Hai Ming Zhao and Tian-Linz Ren, (2013). “A novel flexible Nanogenerator made of ZnO nanoparticles nd and multiwalled carbon Nano tube”, RSC publishing, 22 pp. 117-123.

[2]. Wen Jong Wu and Bor Shiun Lee, (2012). “Piezoelectric MEMS Power Generators for Vibration Energy Harvesting”,.

[3]. Miller, Lindsay Margaret, (2012). “Micro - scale piezo electric vibration energy harvesting : from fixedfrequency to adaptable frequency devices”, ISBN: 9781267605191, Vol. 74, pp. 1-157.

[4]. Jacob thaysen, (2001). “Cantilever for bio chemical sensing integrated in a micro liquid handling system”, PhD Thesis, Mikroelektronik Centret, pp. 1-131.

[5]. M. Hudson, (2006), The final energy crisis, Environ. Pollut., 15, pp. 677–679.

[6]. W. L. Ma, C. Y. Yang, X. Gong, K. Lee and A. J. Heeger, (2005), “Thermally stable, efficient polymer solar cells with nanoscale control of the inter penetrating network morphology”, Adv. Funct. Mater., 15, pp. 1617–1622.

[7]. J. Mcgowan, (1993), “America Reaps the Wind Harvest”, New Scientist, Vol. 139, pp. 30–33.

[8]. C. Howard – Williams, A. M. Schwarz and V. Reid, (1996). “Patterns of aquatic weed regrowth following mechanical harvesting in New Zealand hydro-lakes”, Hydrobiologia, Vol. 340, pp. 229–234.

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Research Paper

A Tunnel Diode Body Contact SOI MOSFET For Low Power Digital Application

Nitu Rao* , VimalKumar Mishra, R. K. Chauhan*

* PG Scholar, Department of Electronics and Communication Engineering, Madan Mohan Malaviya University of Technology, UP, India.

Research Scholar, Department of Electronics and Communication Engineering, Madan Mohan Malaviya University of Technology, UP, India.

* Professor, Department of Electronics and Communication Engineering, Madan Mohan Malaviya University of Technology, UP, India.

Rao, N., Mishra, V.K., and Chauhan, R.K. (2015). A Tunnel Diode Body Contact SOI MOSFET For Low Power Digital Application. i-manager's Journal on Electronics Engineering, 5(3), 35-38. https://doi.org/10.26634/jele.5.3.3396

Abstract

In this paper Tunnel Diode Body Contact (TDBC) SOI p-MOSFET with low off-state leakage current is proposed for low power -13 digital application. The device shows off-state current with a drain voltage of 0.5V as about equal to 3.37×10 A -4 9 (33.7pA) and on-state current as about equal to 1.5×10 A (0.15mA) so that on to off-state current ratio is about 10 . This paper also includes the study of different type of SOI MOSFET namely Partially Depleted SOI (PD SOI), Full Depleted SOI (FD SOI) for low power digital application. This paper also includes the comparison between Partially Depleted TDBCS SOI n- MOSFET and proposed TDBC SOI p-MOSFET.

References

[1]. G. E. Moore, (1965). "Cramming more components into integrated circuits," Electronics, Vol. 38, No. 8,

[2]. J.-P. Colinge, C.W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O'Neill, A. Blake, M.White, A.M. Kelleher, B. McCarthy, and R.Murphy, (2010). "Nanowire Transistors without junctions," Nature Nanotechnology, Vol. 5, No. 3, pp. 225–229,

[3]. S. N. Andrew Marshall, (2003). “SOI Design: Analog, Memory and Digital Techniques”. Boston, MA: Kluwer.

[4]. Qiang Chen; Jung-Suk Goo; Ly, T.; Chandrasekaran, K.; Zhi-Yuan Wu; Thuruthiyil, C.; Icel, A.B., (2008). "Off-state leakage current modeling in low-power/highperformance partially-depleted (PD) floating-body (FB) th SOI MOSFETs," 9 International Conference on, Solid-State and Integrated-Circuit Technology, ICSICT 2008, pp. 301- 304.

[5]. Wei, L.; Chen, Z.; Roy, K., (1998). "Design and optimization of double-gate SOI MOSFETs for low voltage low power circuits," Proceedings IEEE International SOI Conference, pp. 69-70.

[6]. J.Chen, J.Luo, Q.Wu, Z.Chai, T.Yu, Y.Dong, and X.Wang, (2011). "A Tunnel Diode Body Contact Structure to Suppress the Floating-Body Effect in Partially Depleted SOI MOSFET," IEEE Electron Device Lett, Vol.32, No. 10,pp. 1346-1348,

[7]. A. Daghighi, M. Osman, and M. Imam, (2008). "An area efficient body contact for low and high voltage SOI MOSFET devices," Solid State Electron., Vol. 52, No. 2, pp. 196–204, Feb.

[8]. L.Esaki, (1976). "Discovery of the tunnel diode," IEEE Trans. Electron Devices, Vol. ED-23, No. 7, pp. 644–647.

[9]. G. A. M. Hurkx, D. B. M. Klaassen, and M. P. G. Knuvers, (1992). "A new recombination model for device simulation including tunneling," IEEE Trans. Electron Devices, Vol. 39.

[10]. S. M. Sze (3rd Ed).(1981): Physics of Semi- conductor Devices.

i-manager's Journal on Electronics Engineering (JELE)

Current Issue Vol. 15 Issue 1

Most Read

Most Cited

Volume 5 Issue 3 March - May 2015

Design of FIR Filter for Efficient FPGA Implementation

S. V. Padmajarani* , 0**

* Professor and HOD, Department of Electronics and Communication Engineering, Sree Venkateswara College of Engineering, A.P, India. ** Principal, Sree Venkateswara College of Engineering and Technology, Chittoor, A.P, India.

Padmajarani, S.V. , and Muralidhar, M. (2015). Design Of FIR Filter For Efficient FPGA Implementation. i-manager's Journal on Electronics Engineering, 5(3), 1-10. https://doi.org/10.26634/jele.5.3.3392

Abstract

References

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An Efficient Architecture For Single Precision Floating Point Multiplier Using Various Algorithms

K. Charan Kumar* , Sunil Kumar K**

* Assistant Professor, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College (Autonomous), Tirupati. ** B.E Student, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College (Autonomous), Tirupati.

Kumar, K.C., and Kumar, K.S., (2015). An Efficient Architecture For Single Precision Floating Point Multiplier Using Various Algorithms. i-manager's Journal on Electronics Engineering, 5(3), 11-21. https://doi.org/10.26634/jele.5.3.3393

Abstract

References

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An Efficient Design Of XOR Gate And Its Applications Using QCA

D. Ajitha* , K. V. Ramanaiah**, V. Sumalatha***

Ajitha , D., Ramanaiah, K.V., and Sumalatha, V. (2015). An Efficient Design Of XOR Gate And Its Applications Using QCA. i-manager's Journal on Electronics Engineering, 5(3), 22-29. https://doi.org/10.26634/jele.5.3.3394

Abstract

References

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A Novel Pliant Nanogenerator Made Of PDMS and ZnO Nanoparticles

Mareddi Bharathkumar* , Palagani Yellappa**, D. Revanth***

*-*** M.Tech Student, VLSI, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College, Tirupathi.

Bharathkumar, M., Yellappa, P., and Revanth, D. (2015). A Novel Pliant Nanogenerator Made Of PDMS and ZnO Nanoparticles. i-manager's Journal on Electronics Engineering, 5(3), 30-34. https://doi.org/10.26634/jele.5.3.3395

Abstract

References

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A Tunnel Diode Body Contact SOI MOSFET For Low Power Digital Application

Nitu Rao* , VimalKumar Mishra**, R. K. Chauhan***

Rao, N., Mishra, V.K., and Chauhan, R.K. (2015). A Tunnel Diode Body Contact SOI MOSFET For Low Power Digital Application. i-manager's Journal on Electronics Engineering, 5(3), 35-38. https://doi.org/10.26634/jele.5.3.3396

Abstract

References

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* Professor and HOD, Department of Electronics and Communication Engineering, Sree Venkateswara College of Engineering, A.P, India.

** Principal, Sree Venkateswara College of Engineering and Technology, Chittoor, A.P, India.

* Assistant Professor, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College (Autonomous), Tirupati.

** B.E Student, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College (Autonomous), Tirupati.

D. Ajitha* , K. V. Ramanaiah, V. Sumalatha*

Mareddi Bharathkumar* , Palagani Yellappa, D. Revanth*

Nitu Rao* , VimalKumar Mishra, R. K. Chauhan*