Dual Frequency Circular Shaped Two Port MIMO Antenna
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Dual Frequency Circular Shaped Two Port MIMO Antenna
Quantum Dot Cellular Automata (QCA) is an emerging nanotechnology in the field of Quantum electronics for low power consumption and high speed of operational phenomenon. Such type of circuit can be used in many digital applications where CMOS [Complementary Metal Oxide Semiconductor] circuits cannot be used due to high leakage and low switching speed. Also, reversible logic is becoming a more and more prominent technology having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. Reversibility plays an important role when energy efficient computations are considered. By combining both of these low power and area efficient QCA technologies, the author can make a new generation low power system. In this paper, reversible eight-bit parallel binary adder/Subtractor using QCA has been proposed. This method reduces the total area used compared to the normal CMOS based structures and reduces power dissipation by using reversible logic gates.
In CMOS [Complementary Metal Oxide Semiconductor] integrated circuits design, scaling is challenged by higher power consumption. The significant growth in power dissipation has occurred mainly due to the higher clock speeds in addition to the smaller process geometries. The transistor packaging density and functionality on a chip is improved by scaling. The speed and frequency of operation is increased due to scaling and hence higher performance is achieved. When the technology scales down, then the leakage current increases exponentially. In 90 nm and below technologies, leakage power constitutes 30-40% of total power dissipation. In this paper, a dual sleep transistor approach is used for reducing the power dissipation of ring counter circuit with minimum possible area. The simulations were done using Micro wind Layout Editor and DSCH [Digital Schematic Editor] software.
The high speed dual modulus prescaler is one of the important functional blocks in frequency synthesizers. The dual modulus prescaler design is the bottleneck of the synthesizer, as it operates at the highest frequencies and consumes more power than any other circuit blocks of the synthesizer. A dual modulus prescaler (also known as divide-by-N/N+1 counter) normally consists of a divide-by-2/3 prescaler unit followed by several asynchronous divide-by-2 units. Usually, dual modulus prescaler consists of Flip flops and some extra logic implemented using logic gates which determine the terminal count. Here an E-TSPC [Extended True Single Phase Clock] logic based divide-by-2/3 prescaler using pass transistor logic is suitable for low supply voltage (0.9V) and low power applications have been designed and implemented. Here the counting logic and the mode selection control are implemented using a single P-MOS transistor. Thus the critical path is reduced and also increases its working frequency. Simulation results show that, compared with the conventional TSPC [True Single Phase Clock] and E-TSPC based 2/3 prescaler designs as much as 46% in PDP, 24% in operation speed and 44% in area can be achieved by the proposed design. Also the proposed 2/3 prescaler are designed and implemented to design a 32/33 prescaler, 47/48 prescaler and a multimodulus 32/33/47/48 prescaler. The power dissipation of the proposed multimodulus prescaler is lesser than the existing multimodulus prescaler designs shown by the simulation results.
Scaling of the CMOS [Complementary Metal Oxide Semiconductor] technology associated with gate oxide thickness has become a major barrier for the design of circuit in nanoscale Static Random Access Memory (SRAM), especially in lower voltages. The operation of SRAM arrays are critical in reducing the power consumption. The Gate Oxide Breakdown caused by excessive electric field in the gate oxide causes increased vulnerability of the circuit performance, during breakdown. The devices are characterized by increased minimum voltage due to increase the static write failure as the voltage decreases. The design circuits were schematized using the DSCH2 schematic design tool, and their layouts were generated with the Micro wind 2 VLSI layout CAD tool. The proposed structures are simulated using Xilinx ISE design suite.
In this paper, Wallace tree multiplier using the constant delay logic style and less number of transistors were designed and analyzed. Constant Delay (CD) logic provides low power consumption and to adjust the window width of the clock pulse, CD logic produces quick output evaluation before the input arrival for operation. Using these features, performance is good compared to normal static and dynamic logic. In this design, the timing block and logic block are implemented to reduce the static power dissipation and also to reduce the unwanted glitch in the output. This experimental result shows smaller power consumption and reduced chip area compared to the existing design.
