References
[1]. Fahad Ahmed and Linda Milor, (2012). “Analysis and
On-Chip Monitoring of Gate Oxide Breakdown in SRAM
Cells” IEEE transactions on Very Large Scale Integration
(VLSI) systems, Vol. 20, No. 5.
[2]. Jaeyong Chung, ,Joonsung Parkand Jacob A.
Abraham, (2011). “A Built-In Repair Analyzer With Optimal
Repair Rate for Word-Oriented Memories” IEEE
transactions on Very Large Scale Integration (VLSI)
systems.
[3]. W. Jeong, J. Lee, T. Han, K. Lee, and S. Kang, (2010).
“An advanced BIRA for memories with an optimal repair
rate and fast analysis speed by using a branch analyzer,”
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., Vol.
29, No. 12, pp. 2014–2026.
[4]. P. Oehler, A. Bosio, G. D. Natale, and S. Hellebrand,
(2008). “A modular memory BIST for optimized memory
repair,” in Proc. Int. On-Line Test. Symp., pp. 171–172.
[5]. A. Kerber, M. Rohner, T. Pompl, R. Duschi, and M.
Kerber, (2007). “Lifetime prediction for CMOS devices with
ultra-thin gate oxides based on progressive breakdown,”
in Proc. IEEE Int. Reliab. Phys. Symp., pp.217–220.
[6]. M. Rohner, A. Kerber, and M. Kerber (2006), “Voltage
acceleration of TDB and its correlation to post breakdown
conductivity of N- and P-channel MOSFETs,” in Proc. IEEE
Int. Reliab. Phys. Symp., 2006, pp. 76–8.
[7]. Rasras . M, Kaczer . B, Degraeve . R, Van de Mieroop .
K, Roussel P . J, and Groeseneken .G (2002). 'Impact of
MOSFET gate oxide breakdown on digital circuit operation
and reliability,' IEEE Trans. Electron Devices, Vol. 49, No. 3,
pp. 500–506. (1999).
[8]. Stathis. J, (1999). 'Percolation models for gate oxide
breakdown 'J. Appl. Phys., Vol. 86, pp. 5757–5766.
[9]. E.Wu, E. Nowak, J. Aitken, W. Abadeer, L. K. Han, and
S. Lo, (1998). “Structural dependence of dielectric breakdown in ultra-thin gate oxides and its relationship to
soft breakdown modes and device failure,” in Proc.IEEE
Int. Electron Devices Meet., pp. 187–190.
[10]. Wu . E, Nowak .E, Aitken . J, Abadeer . W, Han L . K,
and Lo . S (1998). 'Structural dependence of dielectric
breakdown in ultra-thin gate oxides and its relationship to soft breakdown modes and device failure,' in Proc. IEEE
Int. Electron Devices Meet., pp. 187–190.
[11]. J. Segura and A. Rubio,(1997). “A detailed analysis of
CMOS SRAM's with gate oxide short defects,” IEEE J. Solid-
State Circuits, Vol. 32, No. 10, pp. 1543–1550.
