Comparative Analysis of Digital Circuits in CNTFET and CMOS Technology: A Review
Side Lobe Suppression for Polyphase Codes in Radar
Design of Radix-2 FFT with MDC And Vedic Multiplier for High-Speed Applications
Advanced Deep Learning Architectures for Automated Silicon Wafer Defect Detection with Synthetic Data Augmentation
Chipsetron-Ultracore VX: A Heterogeneous VLSI-Based Controller for Intelligent IoT, Automation, and Real-Time Edge Systems
The Impact of Substrate Doping Concentration on Electrical Characteristics of 45nm Nmos Device
Method of 2.5 V RGMII Interface I/O Duty Cycle and Delay Skew Enhancement
A Study on Globally Asynchronous and locally Synchronous System
Performance Analysis of Modified Source Junctionless Fully Depleted Silicon-on-Insulator MOSFET
Automatic Accident Detection and Tracking of Vehicles by Using MEMS
This paper reviews in depth a procedure to compare the performance of CNTFET and MOSFET devices through the design of a SRAM cell. The results indicate that both technologies enable the realization of low-power devices, with CNTFET technology exhibiting higher speed. Comparative simulations highlight significant improvements in switching delay and energy efficiency when operating in the sub-threshold region using CNTFETs. The findings confirm CNTFET suitability for ultra-low-power and high-frequency applications, positioning it as a strong alternative to traditional CMOS in next-generation memory architectures.
Radar systems rely on effective sidelobe suppression to concentrate energy on the primary lobe, ensuring accurate target detection and minimizing false identifications. Reducing sidelobe levels improves the radar system's capacity to detect weak or far-off objects by helping it differentiate between real targets and background noise. This paper focuses on improving radar signal processing by suppressing side lobes in polyphase codes, which are commonly used in radar systems for pulse compression and waveform design. To address this, in this paper a novel hybrid optimisation approach has been proposed combining Particle Swarm Optimization (PSO) and the Grey Wolf Optimization (GWO) to design polyphase codes with significantly reduced sidelobes. This approach combines the global search efficiency of PSO with the local refinement capabilities of GWO, achieving superior sidelobe suppression while preserving resolution and detection accuracy. The suggested method has been evaluated in regard to suppression effectiveness and computational efficiency by simulating the various optimisation techniques in MATLAB, demonstrating its superiority over traditional windowing techniques and single optimisation algorithms like the genetic algorithm. This novel approach enhances radar performance by reducing interference, improving target discrimination, and increasing resilience against jamming, making it a robust solution for modern radar applications.
Radix-2, radix-4, and radix-2k are some variations of the Fast Fourier Transform (FFT) algorithm, which is used to calculate the Discrete Fourier Transform (DFT) of a sequence. Among these, the radix-2k algorithm is particularly noteworthy because of its low-power requirements, versatility, and straightforward control logic. To provide a simplified butterfly unit with low memory requirements, the suggested radix-2k architecture uses a Multiple Delay Commutator (MDC). Data shifting along the delay line is controlled by an input scheduling algorithm, which also helps to reduce power usage. To support high-speed applications, this work proposes a radix-2² FFT design with a Vedic multiplier. The design is implemented on a Xilinx Virtex-5 FPGA board for 8-point, 16-point, 512-point, and 1024-point FFTs. In particular, the 1024- point Radix-2² FFT architecture uses 121 registers, 11,629 LUTs, and 5,515 slices to achieve a delay of 42.102 ns. Integration of a Vedic multiplier within the butterfly unit resulted in improved operational performance and reduction in area. The performance analysis in terms of energy and latency was also compared with different adders.
The semiconductor industry needs defect-free silicon wafers to make integrated circuits, as even small flaws can reduce yield and cause financial losses. Traditional inspection methods, such as rule-based image processing and manual checks, are time-consuming, error-prone, and inflexible. This study proposes a deep learning framework for automatic wafer defect classification using advanced CNN models and generative data augmentation to fix class imbalance and improve accuracy. The WM-811K dataset with 811,457 wafer maps was reorganized into four classes: Redundant, Crystal, Mechanical, and Defect-Free. Three baseline models (WDD-Net, MobileNet-V2, and VGG-16) were tested, with VGG-16 reaching 80% accuracy. Further experiments using deeper models (VGG-19, GoogleNet) and StyleGAN-based augmentation improved performance, especially for rare defect types. GoogleNet achieved a good balance of accuracy and efficiency, while MobileNet-V2 gave the highest accuracy (92.42%) and recall (92.41%). VGG-19 also showed strong generalization (F1-score: 90.41%), proving that deep CNNs and GAN-based augmentation are effective for wafer defect detection.
The growing complexity of embedded systems and IoT applications demands high-performance, energy-efficient, and versatile hardware platforms. This paper presents Chipsetron, a custom-designed VLSI microcontroller built around a proprietary 32-bit processor core tailored for modern automation, robotics, and edge computing environments. Chipsetron integrates advanced architectural features, including a pipelined RISC core, an embedded GPU for parallel data processing, and a comprehensive interrupt management system with Non-Maskable Interrupt (NMI) support for real-time fault handling. It offers extensive peripheral connectivity, including 32 GPIOs, UART, SPI, I2C, eight PWM channels, a 10-channel 12-bit ADC, and a DAC for analog output. Emphasizing both computational power and system resilience, Chipsetron supports seamless interaction with sensors, actuators, and communication modules. The chip is designed to operate efficiently in power-sensitive environments while offering scalability for both prototyping and deployment. Simulation-based validation confirms its performance and responsiveness, positioning Chipsetron as a robust platform for intelligent embedded applications in domains such as smart infrastructure, environmental monitoring, and autonomous systems.
