i-manager Publications

Advanced Deep Learning Architectures for Automated Silicon Wafer Defect Detection with Synthetic Data Augmentation

Kakarla Deepti*

Department of Elelctronics and Communication Engineering, Vasavi College of Engineering, Hyderabad, India.

Periodicity:October - December'2025

Abstract

The semiconductor industry needs defect-free silicon wafers to make integrated circuits, as even small flaws can reduce yield and cause financial losses. Traditional inspection methods, such as rule-based image processing and manual checks, are time-consuming, error-prone, and inflexible. This study proposes a deep learning framework for automatic wafer defect classification using advanced CNN models and generative data augmentation to fix class imbalance and improve accuracy. The WM-811K dataset with 811,457 wafer maps was reorganized into four classes: Redundant, Crystal, Mechanical, and Defect-Free. Three baseline models (WDD-Net, MobileNet-V2, and VGG-16) were tested, with VGG-16 reaching 80% accuracy. Further experiments using deeper models (VGG-19, GoogleNet) and StyleGAN-based augmentation improved performance, especially for rare defect types. GoogleNet achieved a good balance of accuracy and efficiency, while MobileNet-V2 gave the highest accuracy (92.42%) and recall (92.41%). VGG-19 also showed strong generalization (F1-score: 90.41%), proving that deep CNNs and GAN-based augmentation are effective for wafer defect detection.

Keywords

Silicon Wafer Defect Detection, Convolutional Neural Networks, GoogleNet, VGG-19, Style GAN, Semiconductor Manufacturing.

How to Cite this Article?

Deepti, K. (2025). Advanced Deep Learning Architectures for Automated Silicon Wafer Defect Detection with Synthetic Data Augmentation. i-manager’s Journal on Electronics Engineering, 16(1), 31-41.

References

[1]. Cha, J., & Jeong, J. (2022). Improved U-Net with residual attention block for mixed-defect wafer maps. Applied Sciences, 12(4), 2209.

[2]. Chen, S., Zhang, Y., Yi, M., Shang, Y., & Yang, P. (2021). AI classification of wafer map defect patterns by using dual-channel convolutional neural network. Engineering Failure Analysis, 130, 105756.

[3]. Cheon, S., Lee, H., Kim, C. O., & Lee, S. H. (2019). Convolutional neural network for wafer surface defect classification and the detection of unknown defect class. IEEE Transactions on Semiconductor Manufacturing, 32(2), 163-170.

[4]. Doss, R., Ramakrishnan, J., Kavitha, S., Ramkumar, S., Charlyn Pushpa Latha, G., & Ramaswamy, K. (2022). Classification of Silicon (Si) wafer material defects in semiconductor choosers using a deep learning shufflenet v2 CNN model. Advances in Materials Science and Engineering, 2022(1), 1829792.

[5]. Howard, A. G., Zhu, M., Chen, B., Kalenichenko, D., Wang, W., Weyand, T., & Adam, H. (2017). Mobilenets: Efficient convolutional neural networks for mobile vision applications. arXiv preprint arXiv:1704.04861.

[6]. Howard, A., Sandler, M., Chu, G., Chen, L. C., Chen, B., Tan, M., & Adam, H. (2019). Searching for mobilenetv3. In Proceedings of the IEEE/CVF International Conference on Computer Vision (pp. 1314-1324).

[7]. Hu, J., Shen, L., & Sun, G. (2018). Squeeze-and- excitation networks. In Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition (pp. 7132-7141).

[8]. Jin, C. H., Kim, H. J., Piao, Y., Li, M., & Piao, M. (2020). Wafer map defect pattern classification based on convolutional neural network features and error- correcting output codes. Journal of Intelligent Manufacturing, 31(8), 1861-1875.

[9]. Kahng, H., & Kim, S. B. (2020). Self-supervised representation learning for wafer bin map defect pattern classification. IEEE Transactions on Semiconductor Manufacturing, 34(1), 74-86.

[10]. Kang, H., & Kang, S. (2021). A stacking ensemble classifier with handcrafted and convolutional features for wafer map pattern classification. Computers in Industry, 129, 103450.

[11]. Khan, S. H., Hayat, M., Bennamoun, M., Sohel, F. A., & Togneri, R. (2017). Cost-sensitive learning of deep feature representations from imbalanced data. IEEE Transactions on Neural Networks and Learning Systems, 29(8), 3573-3587.

[12]. Kim, E. S., Choi, S. H., Lee, D. H., Kim, K. J., Bae, Y. M., & Oh, Y. C. (2021). An oversampling method for wafer map defect pattern classification considering small and imbalanced data. Computers & Industrial Engineering, 162, 107767.

[13]. Kyeong, K., & Kim, H. (2018). Classification of mixed- type defect patterns in wafer bin maps using convolutional neural networks. IEEE Transactions on Semiconductor Manufacturing, 31(3), 395-402.

[14]. Lee, K. B., Cheon, S., & Kim, C. O. (2017). A convolutional neural network for fault classification and diagnosis in semiconductor manufacturing processes. IEEE Transactions on Semiconductor Manufacturing, 30(2), 135-142.

[15]. Ma, N., Zhang, X., Zheng, H. T., & Sun, J. (2018). Shufflenet v2: Practical guidelines for efficient CNN architecture design. In Proceedings of the European Conference on Computer Vision (ECCV) (pp. 116-131).

[16]. Nakazawa, T., & Kulkarni, D. V. (2019). Anomaly detection and segmentation for wafer defect patterns using deep convolutional encoder–decoder neural network architectures in semiconductor manufacturing. IEEE Transactions on Semiconductor Manufacturing, 32(2), 250-256.

[17]. Sandler, M., Howard, A., Zhu, M., Zhmoginov, A., & Chen, L. C. (2018). Mobilenetv2: Inverted residuals and linear bottlenecks. In Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition (pp. 4510- 4520).

[18]. Saqlain, M., Abbas, Q., & Lee, J. Y. (2020). A deep convolutional neural network for wafer defect identification on an imbalanced dataset in semiconductor manufacturing processes. IEEE Transactions on Semiconductor Manufacturing, 33(3), 436-444.

[19]. Saqlain, M., Jargalsaikhan, B., & Lee, J. Y. (2019). A voting ensemble classifier for wafer map defect patterns identification in semiconductor manufacturing. IEEE Transactions on Semiconductor Manufacturing, 32(2), 171-182.

[20]. Tan, M., & Le, Q. (2019). Efficientnet: Rethinking model scaling for convolutional neural networks. In International Conference on Machine Learning (pp. 6105-6114). PMLR.

[21]. Tan, M., & Le, Q. (2021). Efficientnetv2: Smaller models and faster training. In International Conference on Machine Learning (pp. 10096-10106). PMLR.

[22]. Tang, Y., Zhang, Y. Q., Chawla, N. V., & Krasser, S. (2008). SVMs modeling for highly imbalanced classification. IEEE Transactions on Systems, Man, and Cybernetics, Part B (Cybernetics), 39(1), 281-288.

[23]. Tsai, T. H., & Lee, Y. C. (2020). A light-weight neural network for wafer map classification based on data augmentation. IEEE Transactions on Semiconductor Manufacturing, 33(4), 663-672.

[24]. Tsai, T. H., & Wang, C. Y. (2025). Wafer map defect classification using deep learning framework with data augmentation on imbalance datasets. EURASIP Journal on Image and Video Processing, 2025(1), 6.

[25]. Wang, J., Xu, C., Yang, Z., Zhang, J., & Li, X. (2020). Deformable convolutional networks for efficient mixed- type wafer defect pattern recognition. IEEE Transactions on Semiconductor Manufacturing, 33(4), 587-596.

[26]. Wu, M. J., Jang, J. S. R., & Chen, J. L. (2014). Wafer map failure pattern recognition and similarity ranking for large- scale data sets. I EEE Transactions on Semiconductor Manufacturing, 28(1), 1-12.

[27]. Yoon, S., & Kang, S. (2022). Semi-automatic wafer map pattern classification with convolutional neural networks. Computers & Industrial Engineering, 166, 107977.

[28]. Yu, N., Chen, H., Xu, Q., Hasan, M. M., & Sie, O. (2023). Wafer map defect patterns classification based on a lightweight network and data augmentation. CAAI Transactions on Intelligence Technology, 8(3), 1029-1042.

[29]. Zhang, X., Zhou, X., Lin, M., & Sun, J. (2018). Shufflenet: An extremely efficient convolutional neural network for mobile devices. In Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition (pp. 6848-6856).

[30]. Zheng, H., Sherazi, S. W. A., Son, S. H., & Lee, J. Y. (2021). A deep convolutional neural network-based multi- class image classification for automatic wafer map failure recognition in semiconductor manufacturing. Applied Sciences, 11(20), 9769.

Advanced Deep Learning Architectures for Automated Silicon Wafer Defect Detection with Synthetic Data Augmentation

Abstract

Keywords

How to Cite this Article?

References

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