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i-manager's Journal on Circuits and Systems (JCIR)

Current Issue Vol. 12 Issue 1

Unified Power Quality Conditioner Research Study on STEADY - STATE POWER FLOW

Most Cited

Electronic Circuit Design for Electromagnetic Compliance through Problem-Based Learning
Trioinformatics: The Innovative and Novel Logic Notation That Defines, Explains, and Expresses the Rational Application of The Law of Trichotomy for Digital Instrumentation and Circuit Design
Design Of a Novel Gated 5T SRAM Cell with Low Power Dissipation in Active and Sleep Mode
A Two Stage Power Optimized Implantable Neural Amplifier Based on Cascoded Structures
An Efficient Hybrid PFSCL based Implementation of Asynchronous Pipeline

Volume 5 Issue 3 June - August 2017

Research Paper

Performance Analysis of Adder Circuits Using FINFET'S

V. Nancharaiah * , R. Ramana Reddy, N. Balaji*

* Research Scholar, Department of Electronics and Communication Engineering, JNTU Kakinada, India.

Professor and Head, Department of Electronics and Communication Engineering, MVGR College of Engineering (A), Viziangaram. India.

* Professor and Vice-principal, Department of Electronics and Communication Engineering (Admin), UCOE Narasaraopeta, JNTUK, India

Vejendla, N., Reddy, P. R., Balaji, N. (2017). Performance Analysis of Adder Circuits Using FINFET'S. i-manager’s Journal on Circuits and Systems, 5(3), 1-9. https://doi.org/10.26634/jcir.5.3.13811

Abstract

Due to scaling of conventional MOS transistors, leakage currents are increasing which leads to increase in power dissipation. Increase in power dissipation puts limit on scaling. To overcome the power dissipation problem, conventional MOS transistors are replaced with FinFETs. FinFETs have low leakage currents which reduce power dissipation. In this paper the focus is on the implementation of different full adder circuits using FinFETs. Comparisons are made between CMOS and FinFET implementation of Hybrid Full Adder, 14 Transistor Full Adder, GDI based Full Adder, and 10 transistor Full Adder using 32 nm and 45 nm technology models. FinFET implementation achieves low power and high speed compared to CMOS implementation.

References

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Research Paper

Performance of Vector Controlled Dual Inverter Fed Open-End Winding Induction Motor Drive Using SVPWM Techniques

M. Ranjit* , T. Brahmananda Reddy, Surya Kalavathi M*

* Assistant Professor, Department of Electrical and Electronics Engineering, VNRVJIET, Bachupally, Hyderabad, Telangana, India.

Head and Professor, Department of Electrical and Electronics Engineering, GPREC, Kurnool, Andhra Pradesh, India.

* Professor, Department of Electrical and Electronics Engineering, JNTUH, Kukatpally, Hyderabad, Telangana, India.

Ranjit, M., Reddy, T. B., Suryakalavathi, M. (2017). Performance of Vector Controlled Dual Inverter Fed Open-End Winding Induction Motor Drive Using SVPWM Techniques. i-manager’s Journal on Circuits and Systems, 5(3), 10-16. https://doi.org/10.26634/jcir.5.3.13812

Abstract

In this paper, decoupled space vector based PWM techniques are proposed for vector controlled open-end winding induction motor drive. The proposed decoupled PWM techniques reduce the ripples in both stator current as well as in torque, unlike conventional PWM techniques. All the proposed decoupled SVPWM techniques are obtained by phase shifting the one inverter reference sinusoids by 180⁰ with respect to the other inverter reference sinusoids. A commonmode voltage is identified in the open-end winding induction motor drive. The proposed PWM techniques also reduce the common-mode voltage by great extent. To demonstrate the proposed work, several simulation studies have been carried out using MATLAB/SIMULINK and the corresponding results are reported and compared

References

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Review Paper

Fault Location Estimation Systems: A Critical Review

A. Sanad Ahmed* , Mahmoud Abdallah Attia, Nabil M. Hamed*, Almoataz Y. Abdelaziz****

* Deputy Project Manager, Siemens S.A.E, Egypt.

,* Assistant Professor, Department of Electric Power and Machines, Ain Shams University, Egypt.

**** Professor, Department of Electrical Power Engineering, Ain Shams University, Egypt.

Sanad, A. A., Attia, M. A., Hamed, N. M., Abdelaziz, A. Y. (2017). Fault Location Estimation Systems: A Critical Review. i-manager’s Journal on Circuits and Systems, 5(3), 17-30. https://doi.org/10.26634/jcir.5.3.13813

Abstract

Energy reliability is a critical aspect nowadays in energy management. Especially transmission system is considered a very essential part in the grid. Using transmission system all customers can get the energy needed for all applications on all voltage levels. So, if a fault occurs in the transmission system, this will lead to outages at customer side affecting all applications, such as hospitals, factories, schools, universities, and houses. To keep the transmission system reliable, all types of fault should be detected and located in a very short period to clear the fault and restore the energy again. This introduces the topic of fault location estimation in smart grids, which is not a new topic, but it is optimized and enhanced nowadays using the available technology. This paper presents several techniques used to detect fault location using different methodologies and algorithms, comparing them all, and finally stating the conclusion.

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Survey Paper

Electromigration – A Brief Survey

Satigouda Patil* , H. P. Rajani**

* Research Scholar, VTU, Belgaum, India

** Professor, Department of Electronics and Communication Engineering, KLESCET, Belagavi, India.

PATIL, S., and Rajani, H. P. (2017). Electromigration – A Brief Survey. i-manager’s Journal on Circuits and Systems, 5(3), 31-37. https://doi.org/10.26634/jcir.5.3.13814

Abstract

As the feature size shrinks, Electromigration (EM) becomes a more critical reliability issue in IC design. EM around the via structures account for much of the reliability problems in ICs [13]. Electromigration is increasingly relevant to physical design of the electronic circuits. It is caused by excess current density stress in the interconnect. The ongoing reduction of the circuit feature sizes has aggravated the problem over last couple of years. It is therefore an important reliability issue to consider electromigration-related design parameters during physical design as life-span of the chip is defined by how well EM verification is done for that chip. So EM is a very important check to be taken care in reliability checks. Literature deals with different aspect of EM in [1], [2], [10], [21], and [22]. In this paper, an effort is made to review different aspects of EM, solution proposed and scope for improvement. The authors have reviewed and identified various fascinating issues and possible solutions to address them.

References

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[2]. de Paris, L., Posser, G., & Reis, R. (2016, May). Electromigration aware circuits by using special signal nondefault routing rules. In Circuits and Systems (ISCAS), 2016 IEEE International Symposium on (pp. 2795-2798). IEEE.

[3]. Jain, P. & Jain, A. (2011, January). Accurate Estimation of Signal Currents for Reliability Analysis considering Advanced Waveform-Shape effects. In VLSI Design (VLSI Design), 2011 24^th International Conference on (pp. 118- 123). IEEE.

[4]. Kludt, J., Weide-Zaage, K., Ackermann, M., Kovacs, C., & Hein, V. (2014, June). Reliability performance of different layouts of wide metal tracks. In Reliability Physics Symposium, 2014 IEEE International (pp. IT-4). IEEE.

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[8]. Li, X., Huang, B., Qin, J., Zhang, X., Talmor, M., Gur, Z., & Bernstein, J. B. (2005, March). Deep submicron CMOS integrated circuit reliability simulation with SPICE. In Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on (pp. 382-389). IEEE.

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[10]. Lienig, J., & Jerke, G. (2005, January). Electromigration-aware physical design of intergrated th circuits. In VLSI Design, 2005. 18 International Conference on (pp. 77-82). IEEE.

[11]. Maex, K., Stucchi, M., Bamal, M., Grossar, E., Dehaene, W., Papanikolaou, A. et al. (2005, May). Technology aware design and design aware technology. In Integrated Circuit Design and Technology, 2005. ICICDT 2005. 2005 International Conference on (pp. 77-81). IEEE.

[12]. Malucci, R. D. (2013, September). The impact of electro-migration on various contact materials. In Holm th Conference on Electrical Contacts (HOLM), 2013 IEEE 59 (pp. 1-8). IEEE.

[13]. Pak, J., Yu, B., & Pan, D. Z. (2015, January). Electromigration-aware redundant via insertion. In Design Automation Conference (ASP-DAC), 2015 20^th Asia and South Pacific (pp. 544-549). IEEE.

[14]. Papanikolaou, A., Wang, H., Miranda, M., Catthoor, F., & Dehaene, W. (2008). Reliability issues in deep deep submicron technologies: Time-dependent variability and its impact on embedded system design. In VLSI-SoC: Research Trends in VLSI and Systems on Chip (pp. 119-141). Springer, Boston, MA.

[15]. Posser, G., Mishra, V., Jain, P., Reis, R., & Sapatnekar, S. S. (2016). Cell-internal electromigration: Analysis and pin placement based optimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 35(2), 220-231.

[16]. Reddy, V., Krishnan, A., et al. (2002). Impact of Negative Bias Temperature Instability on Digital Circuit Reliability, Intl. Reliability Physics Symp. (pp. 248–254).

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[19]. VLSI CAD LAB, University of California, Santa Barbara.

[20]. Yang, S. F. & Chien, W. T. K. (2015). Electromigration lifetime optimization by uniform designs and a new lifetime index. IEEE Transactions on Reliability, 64(4), 1158-1163.

[21]. Zhang, Z., Basavalingappa, A., Lloyd, J. R., Tan, J., & Justison, P. (2014, June). Effect of via arrangement on electromigration performance. In Reliability Physics Symposium, 2014 IEEE International (pp. IT-6). IEEE.

[22]. Zhao, X. (2016, March). Exploration on electromigration short length effect of Low-K Cu interconnect. In Semiconductor Technology International Conference (CSTIC), 2016 China (pp. 1-2). IEEE.

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Research Paper

A High Speed Arithmetic Architecture of Parallel Multiplier-Accumulator (MAC) Based on Radix-2 Modified Booth Algorithm

Ishita Verma* , Priyanka Ghosh, Upendra Soni*, Dharmendra Singh****

- UG Scholar, Department of Electronics and Telecommunication Engineering, Shri Shankaracharya Institute of Professional Management and Technology (SSIPMT), Bhilai, India.

-**** Assistant Professor, Department of Electronics and Telecommunication Engineering, Shri Shankaracharya Institute of Professional Management and Technology (SSIPMT), Bhilai, India.

Verma, I., Ghosh , P., Soni, U., and Singh, D. (2017). A High Speed Arithmetic Architecture of Parallel Multiplier-Accumulator (MAC) Based on Radix-2 Modified Booth Algorithm. i-manager’s Journal on Circuits and Systems, 5(3), 38-42. https://doi.org/10.26634/jcir.5.3.13866

Abstract

In this paper, a new architecture is proposed for multiplier and Accumulator to increase the arithmetic operation. Multiplication and accumulation will help in improving the performance of multiplier. The Radix-2 modified booth algorithm is used for the reduction of partial products. The parallel multiplier can be such as radix 2 modified booth algorithm is used to improve the computations; this can be achieved using fewer adder and steps. By using Radix-2 modified booth multiplier algorithm the high speed of operation can be achieved.

References

[1]. Aparna, P. R. & Thomas, N. (2012, February). Design and implementation of a high performance multiplier using HDL. In Computing, Communication and Applications (ICCCA), 2012 International Conference on (pp. 1-5). IEEE.

[2]. Baba, S. K. & Rajaramesh, D. (2013). Design and implementation of advanced modified booth encoding multiplier. Int. J. Eng. Sci. Inven., 2(8), 60-68.

[3]. Dally, W. J. & Lacy, S. (1999, March). VLSI architecture: past, present, and future. In Advanced Research in VLSI, 1999. Proceedings. 20^thAnniversary Conference on (pp. 232-241). IEEE.

[4]. Kaur, J. (2013). Design and Implementation of an efficient Modified Booth Multiplier using VHDL. International Journal of Advances in Engineering Sciences, 3(3), 78-81.

[5]. Kiruthika, S., Kumar, R. N., & Valarmathy, D. S. (2013). Comparative Analysis of 4-Bit Multipliers using Low Power 8- Transistor Full Adder Cells. International Journal of Emerging Technology and Advanced Engineering, 3(1), 1488-1492.

[6]. Kudithipudi, D. & John, E. (2005). Implementation of low power digital multipliers using 10 transistor adder blocks. Journal of Low Power Electronics, 1(3), 286-296.

[7]. Kuo, T. H., Lin, H. C., Potter, R. C., & Schupe, D. (1993). Multiple-valued counter. IEEE Transactions on Computers, 42(1), 106-109.

[8]. Marimuthu, C. N. & Thangaraj, P. (December, 2008). Low Power High Performance Multiplier. In ICGST-PDCS (Vol. 8, No. 1).

[9]. Mathew, K., Latha, S. A., Ravi, T., & Logashanmugam, E. (2013). Design and analysis of array multiplier using an area efficient full adder cell in 32 nm CMOS technology. International Journal of Engineering and Science, 2(3), 8-16.

[10]. Namdeo, A. J. P. (2012). Low Power VLSI Techniques using Booth Algorithm for Digital Filter for Hearing aid Applications. International Journal of Engineering and Innovative Technology (IJEIT), 1(2), 109-111.

[11]. Pedram, M. (1999). Power Simulation and Estimation in VLSI Circuits. In VLSI Handbook. CRC Press, Inc.

[12]. Pohane, G. & Sharma, S. (2015). VLSI Designing of High Speed Parallel Multiplier Accumulator Based on Radix 4 Booths Multiplier. Int. Journal of Application or Innovation in Engineering and Management, 4(3), 33-39.

[13]. Poornima, M., Patil, S. K., Shivukumar, S. K., & Sanjay, H. (2013). Implementation of multiplier using vedic algorithm. International Journal of Innovative Technology and Exploring Engineering (IJITEE), 2(6), 219-223.

[14]. Seo, Y. H. & Kim, D. W. (2010). A new VLSI architecture of parallel multiplier–accumulator based on Radix-2 modified Booth algorithm. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18(2), 201-208.

[15]. Swee, K. L. S. & Hiung, L. H. (2012, June). Performance comparison review of 32-bit multiplier designs. In Intelligent and Advanced Systems (ICIAS), 2012 4^th International Conference on (Vol. 2, pp. 836-841). IEEE.

[16]. Vasudev, G. & Hegadi, R. (2012). Design and Development of 8-Bits Fast Multiplier for Low Power Applications. International Journal of Engineering and Technology, 4(6), 774-780.

i-manager's Journal on Circuits and Systems (JCIR)

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Volume 5 Issue 3 June - August 2017

Performance Analysis of Adder Circuits Using FINFET'S

V. Nancharaiah * , R. Ramana Reddy**, N. Balaji***

Vejendla, N., Reddy, P. R., Balaji, N. (2017). Performance Analysis of Adder Circuits Using FINFET'S. i-manager’s Journal on Circuits and Systems, 5(3), 1-9. https://doi.org/10.26634/jcir.5.3.13811

Abstract

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Performance of Vector Controlled Dual Inverter Fed Open-End Winding Induction Motor Drive Using SVPWM Techniques

M. Ranjit* , T. Brahmananda Reddy**, Surya Kalavathi M***

Ranjit, M., Reddy, T. B., Suryakalavathi, M. (2017). Performance of Vector Controlled Dual Inverter Fed Open-End Winding Induction Motor Drive Using SVPWM Techniques. i-manager’s Journal on Circuits and Systems, 5(3), 10-16. https://doi.org/10.26634/jcir.5.3.13812

Abstract

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Fault Location Estimation Systems: A Critical Review

A. Sanad Ahmed* , Mahmoud Abdallah Attia**, Nabil M. Hamed***, Almoataz Y. Abdelaziz****

* Deputy Project Manager, Siemens S.A.E, Egypt. **,*** Assistant Professor, Department of Electric Power and Machines, Ain Shams University, Egypt. **** Professor, Department of Electrical Power Engineering, Ain Shams University, Egypt.

Sanad, A. A., Attia, M. A., Hamed, N. M., Abdelaziz, A. Y. (2017). Fault Location Estimation Systems: A Critical Review. i-manager’s Journal on Circuits and Systems, 5(3), 17-30. https://doi.org/10.26634/jcir.5.3.13813

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Electromigration – A Brief Survey

Satigouda Patil* , H. P. Rajani**

* Research Scholar, VTU, Belgaum, India ** Professor, Department of Electronics and Communication Engineering, KLESCET, Belagavi, India.

PATIL, S., and Rajani, H. P. (2017). Electromigration – A Brief Survey. i-manager’s Journal on Circuits and Systems, 5(3), 31-37. https://doi.org/10.26634/jcir.5.3.13814

Abstract

References

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A High Speed Arithmetic Architecture of Parallel Multiplier-Accumulator (MAC) Based on Radix-2 Modified Booth Algorithm

Ishita Verma* , Priyanka Ghosh**, Upendra Soni***, Dharmendra Singh****

Verma, I., Ghosh , P., Soni, U., and Singh, D. (2017). A High Speed Arithmetic Architecture of Parallel Multiplier-Accumulator (MAC) Based on Radix-2 Modified Booth Algorithm. i-manager’s Journal on Circuits and Systems, 5(3), 38-42. https://doi.org/10.26634/jcir.5.3.13866

Abstract

References

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V. Nancharaiah * , R. Ramana Reddy, N. Balaji*

M. Ranjit* , T. Brahmananda Reddy, Surya Kalavathi M*

A. Sanad Ahmed* , Mahmoud Abdallah Attia, Nabil M. Hamed*, Almoataz Y. Abdelaziz****

* Deputy Project Manager, Siemens S.A.E, Egypt.

,* Assistant Professor, Department of Electric Power and Machines, Ain Shams University, Egypt.

**** Professor, Department of Electrical Power Engineering, Ain Shams University, Egypt.

* Research Scholar, VTU, Belgaum, India

** Professor, Department of Electronics and Communication Engineering, KLESCET, Belagavi, India.

Ishita Verma* , Priyanka Ghosh, Upendra Soni*, Dharmendra Singh****