Performance Analysis of Adder Circuits Using FINFET'S

V. Nancharaiah *, R. Ramana Reddy**, N. Balaji***
* Research Scholar, Department of Electronics and Communication Engineering, JNTU Kakinada, India.
** Professor and Head, Department of Electronics and Communication Engineering, MVGR College of Engineering (A), Viziangaram. India.
*** Professor and Vice-principal, Department of Electronics and Communication Engineering (Admin), UCOE Narasaraopeta, JNTUK, India
Periodicity:June - August'2017
DOI : https://doi.org/10.26634/jcir.5.3.13811

Abstract

Due to scaling of conventional MOS transistors, leakage currents are increasing which leads to increase in power dissipation. Increase in power dissipation puts limit on scaling. To overcome the power dissipation problem, conventional MOS transistors are replaced with FinFETs. FinFETs have low leakage currents which reduce power dissipation. In this paper the focus is on the implementation of different full adder circuits using FinFETs. Comparisons are made between CMOS and FinFET implementation of Hybrid Full Adder, 14 Transistor Full Adder, GDI based Full Adder, and 10 transistor Full Adder using 32 nm and 45 nm technology models. FinFET implementation achieves low power and high speed compared to CMOS implementation.

 

Keywords

FinFET, CMOS, Hybrid Full Adder, GDI, Power Dissipation, Delay

How to Cite this Article?

Vejendla, N., Reddy, P. R., Balaji, N. (2017). Performance Analysis of Adder Circuits Using FINFET'S. i-manager’s Journal on Circuits and Systems, 5(3), 1-9. https://doi.org/10.26634/jcir.5.3.13811

References

[1]. Abu-Khater, I. S., Bellaouar, A., & Elmasry, M. I. (1996). Circuit techniques for CMOS low-power high-performance multipliers. IEEE Journal of Solid-State Circuits, 31(10), 1535- 1546.
[2]. Abu-Shama, E. & Bayoumi, M. (1995). A new cell for low power adders. Proc. Int. Midwest Symp. Circuits and Systems, 1014–1017. .
[3]. Bhattacharyya, P., Kundu, B., Ghosh, S., Kumar, V., & Dandapat, A. (2015). Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23(10).
[4]. Bui, H. T., Wang, Y., & Jiang, Y. (2002). Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 49(1), 25-30.
[5]. Chandrakasan, A. P. & Brodersen, R. W. (1995). Low Power Digital CMOS Design. Kluwer AcademicPublishers
[6]. Chandrakasan, A. P., Sheng, S., & Brodersen, R. W. (1992). Low power CMOS digital design. IEEE Journal of Solid-State Circuits, 27(4), 473–484.
[7]. Chang, C. H., Gu, J., & Zhang, M. (2005). A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 13(6), 686-695.
[8]. Foroutan, V., Taheri, M., Navi, K., & Mazreah, A. A. (2014). Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style. INTEGRATION, the VLSI Journal, 47(1), 48-61.
9]. Goel, S., Elgamel, M. A., & Bayoumi, M. A. (2003, September). Novel design methodology for highperformance XOR-XNOR circuit design. In Integrated Circuits and Systems Design, 2003. SBCCI 2003. th Proceedings. 16 Symposium on (pp. 71-76). IEEE.
[10]. Goel, S., Gollamudi, S., Kumar, A., & Bayoumi, M. (2004). On the design of low-energy hybrid CMOS 1 -bit full th adder cells, Proceedings of the 47 IEEE International Midwest Symposium on Circuits and Systems, (pp.209-212).
[11]. Goel, S., Kumar, A., & Bayoumi, M. A. (2006). Design of robust, energy-efficient full adders for deepsubmicrometer design using hybrid-CMOS logic style. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(12), 1309-1321.
[12]. Kang, S. M., Leblebici, Y., & Kim, C. (2014). CMOS Digital Integrated Circuits: Analysis & Design (No. EPFLBOOK- 202021). McGraw-Hill Higher Education.
[13]. King, T. J. (2005, May). FinFETs for nanoscale CMOS digital integrated circuits. In Proceedings of the 2005 IEEE/ACM International Conference on Computer-Aided Design (pp. 207-210). IEEE Computer Society.
[14]. Kumar, K. R., Reddy, P. M., Sadanandam, M., Kumar, A. S., & Raju, M. (2017, February). Design of 2T XOR gate based full adder using GDI technique. In Innovative Mechanisms for Industry Applications (ICIMIA), 2017 International Conference on (pp. 10-13). IEEE.
[15]. Kumar, P. & Sharma, R. K. (2016). Low voltage high performance hybrid full adder. Engineering Science and Technology, an International Journal, 19(1), 559-565.
[16]. Lin, J. F., Hwang, Y. T., Sheu, M. H., & Ho, C. C. (2007). A novel high-speed and energy efficient 10-transistor full adder design. IEEE Transactions on Circuits and Systems I: Regular Papers, 54(5), 1050-1059.
[17]. Morgenshtein, A., Fish, A., & Wagner, I. A. (2002). Gate-diffusion input (GDI): A power-efficient method for digital combinatorial circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 10(5), 566-581.
[18]. Morgenshtein, A., Shwartz, I., & Fish, A. (2010, November). Gate diffusion input (GDI) logic in standard CMOS nanoscale process. In Electrical and Electronics th Engineers in Israel (IEEEI), 2010 IEEE 26 Convention of (pp. 000776-000780). IEEE.
[19]. Mukherjee, B., & Ghosal, A. (2015, July). Design and study of a low power high speed full adder using GDI multiplexer. In Recent Trends in Information Systems (ReTIS), nd 2015 IEEE 2 International Conference on (pp. 465-470). IEEE.
[20]. Parameswar, A., Hara, H., & Sakurai, T. (1994, May). A high speed, low power, swing restored pass-transistor logic based multiply and accumulate circuit for multimedia applications. In Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE (pp. 278-281). IEEE.
[21]. Parameswar, A., Hara, H., & Sakurai, T. (1996). A swing restored pass-transistor logic-based multiply and accumulate circuit for multimedia applications. IEEE Journal of Solid-State Circuits, 31(6), 804-809.
[22]. Rabaey, J. M., Chandrakasan, A. P., & Nikolic, B. (2002). Digital Integrated Circuits (Vol. 2). Englewood Cliffs: Prentice Hall.
[23]. Radhakrishnan, D. (2001). Low-voltage low-power CMOS full adder. IEE Proceedings-Circuits, Devices and Systems, 148(1), 19-24.
[24]. Semiconductor Industry Association. (2011). International Technology Roadmap for Semiconductors. Retreived from https://www.semiconductors.org/ clientuploads/Research_Technology/ITRS/2011/2011ExecS um.pdf
[25]. Shalem, R., John, E., & John, L. K. (1999, March). A novel low power energy recovery full adder cell. In VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on (pp. 380-383). IEEE.
[26]. Shams, A. M., & Bayoumi, M. A. (1997, November). A structured approach for designing low power adders. In Signals, Systems, & Computers, 1997. Conference Record of the Thirty-First Asilomar Conference on (Vol. 1, pp. 757- 761). IEEE. .
[27]. Shams, A. M., & Bayoumi, M. A. (2000). A novel highperformance CMOS 1-bit full-adder cell. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 47(5), 478-481.
[28]. Shams, A. M., Darwish, T. K., & Bayoumi, M. A. (2002). Performance analysis of low-power 1-bit CMOS full adder cells. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 10(1), 20-29.
[29]. Shoba, M., & Nakkeeran, R. (2016). GDI based full adders for energy efficient arithmetic applications. Engineering Science and Technology, an International Journal, 19(1), 485-496.
[30]. Vai, M. M. (2001). VLSI Design. Taylor & Francis
[31]. Vesterbacka, M. (1999). A 14-transistor CMOS full adder with full voltage-swing nodes. In Signal Processing Systems, 1999. SiPS 99. 1999 IEEE Workshop on (pp. 713- 722). IEEE.
[32]. Wairya, S., Singh, G., Nagaria, R. K., & Tiwari, S. (2011, December). Design analysis of XOR (4T) based low voltage CMOS full adder circuit. In Engineering (NUiCONE), 2011 Nirma University International Conference on (pp. 1-7). IEEE.
[33]. Wang, J. M., Fang, S. C., & Feng, W. S. (1994). New efficient designs for XOR and XNOR functions on the transistor level. IEEE Journal of Solid-State Circuits, 29(7), 780-786.
[34]. Weste, N., & Harris, D. (2005). CMOS VLSI Design. Pearson Wesley.
[35]. Zhuang, N., & Wu, H. (1992). A new design of the CMOS full adder. IEEE Journal of Solid-State Circuits, 27(5), 840-844.
If you have access to this article please login to view the article or kindly login to purchase the article

Purchase Instant Access

Single Article

North Americas,UK,
Middle East,Europe
India Rest of world
USD EUR INR USD-ROW
Online 15 15

Options for accessing this content:
  • If you would like institutional access to this content, please recommend the title to your librarian.
    Library Recommendation Form
  • If you already have i-manager's user account: Login above and proceed to purchase the article.
  • New Users: Please register, then proceed to purchase the article.