Loss Distribution Methodology with a Sense Of Emission Dispatch
Low Power Optimization Technique Based Linear Feedback Shift Register
Leakage Power Reduction Using Multi Modal Driven Hierarchical Power Mode Switches
Validation of IOV chain using OVM Technique
Performance of Continuous and Discontinuous Space Vector Pwm Technique for Open End Winding Induction Motor Drive
Electronic Circuit Design for Electromagnetic Compliance through Problem-Based Learning
Trioinformatics: The Innovative and Novel Logic Notation That Defines, Explains, and Expresses the Rational Application of The Law of Trichotomy for Digital Instrumentation and Circuit Design
Design Of a Novel Gated 5T SRAM Cell with Low Power Dissipation in Active and Sleep Mode
A Two Stage Power Optimized Implantable Neural Amplifier Based on Cascoded Structures
An Efficient Hybrid PFSCL based Implementation of Asynchronous Pipeline
In the field of nanotechnology, leakage noise and ground reflections have become important considerations in the design of VLSI circuits. Power leakage is a serious problem, especially in handheld and portable battery powered devices, due to critical battery life. Ground bounce can cause false transactions, resulting in incorrect values in digital circuits. In nanoscale VLSIs, the problem of reducing leakage and ground bounce needs to be addressed in order to improve circuit performance. In this paper, two power gating techniques to minimize leakage and ground bounce are proposed. Leakage power and ground bounce noise are estimated for ISCAS'85 benchmark circuits and simulation results reveal that the proposed techniques mitigate maximum of 79% leakage power and 60% ground bounce than conventional techniques.
In this paper, a cascade topology of a multilevel reverse voltage (RV) inverter has been proposed to improve multilevel performance by compensating for the shortcomings of two-level and conventional multilevel inverters (MLI). This topology requires less number of parts compared to existing MLI's particularly in higher levels with less gate drives and carrier signals. Therefore, the total cost and complication are greatly reduced, predominantly for higher output voltage levels. The suggested topology can have the improved performance by employing the most relevant control and modulation methods based on multiple space vector references with single U-type carrier wave. The paper persistently attempts to present the analysis carried out using space vector modified PWM control methods based on several references for the topology of a single-phase seven-level RV inverter in terms of total harmonic distortion (THD) and fundamental RMS voltage. Finally, simulation results are included to test the effectiveness of the proposed RV topology. A hardware setup has been developed to match the simulation results of a single-phase seven-level FPGA-based pulse-generated RV cascade inverter.
This paper presents a 4-stage pipelined analog to digital converter (ADC) architecture with a 4-bit resolution per each stage, enabled with the help of a successive approximation register (SAR) based sub-ADC. Successive approximation register (SAR) ADC architectures are popular for achieving high energy efficiency, low power applications but they suffer from resolution and speed limitations. To overcome the speed limitations of SAR ADC we propose the systematic design approach of a low-power, high-speed pipelined ADC. The power consumptions of the capacitive digital to analog converter (DAC), two stage FinFET comparator with output inverter of the proposed ADC are lower than those of a conventional ADC. ADC is designed in 22 nm FinFET technology with medium sampling rate and 16-bit resolution are achieved.
This article proposes new schemes for XOR/XNOR and concurrent XOR-XNOR functions. Due to low output capacitance and low short-circuit power dissipation, these circuits are well optimized in terms of power consumption and delay. Six novel hybrid 1-bit full adder (FA) circuits based on full-swing XOR/XNOR gates are also available. In terms of speed, power consumption, power delay product (PDP), driving ability, etc., each of these circuits has unique benefits. Extensive Mentor Graphics is used to study the performance of the designs. The simulation findings, which are based on a 130 nm CMOS process technology model, show that the suggested designs outperform previous FA solutions in terms of speed and power. To improve the PDP of the circuits, a novel transistor size strategy is provided. The approach employs a numerical computing particle swarm optimization algorithm to reach the target PDP value with fewer repetitions. The circuits are examined in terms of supply and threshold voltage fluctuations, output capacitance, input noise immunity, and transistor size.
This study discusses the Unified Power Flow Controller (UPFC) to improve power system voltage stability. With its unique ability to manage parallel flows of real and reactive power on a transmission line, as well as adjust the voltage on the bus, where it affects the stability of the power system. This will provide much-needed flexibility to power system operators to meet the requirements that the deregulated power system would impose. The shunt converter regulates the transmission line reactive power flow and the DC link voltage in UPFC's fundamental control approach. The series converter controls the actual power flow in the transmission line as well as the UPFC bus voltages. The performance of UPFC to regulate the flow of power across the transmission line is examined in this research. Real power, reactive power, and voltage over the transmission line cannot be managed without UPFC. The UPFC circuit model is created in MATLAB/Simulink utilizing rectifier and inverter circuits, and simulation results are shown to verify the model.
