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Implementation of Pipelined ADC using 22 nm FinFET Technology

M. Chandra Sekhar Reddy*

Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College, Tirupati, Andhra Pradesh, India.

Periodicity:July - December'2021
DOI : https://doi.org/10.26634/jcir.9.2.15094

Abstract

This paper presents a 4-stage pipelined analog to digital converter (ADC) architecture with a 4-bit resolution per each stage, enabled with the help of a successive approximation register (SAR) based sub-ADC. Successive approximation register (SAR) ADC architectures are popular for achieving high energy efficiency, low power applications but they suffer from resolution and speed limitations. To overcome the speed limitations of SAR ADC we propose the systematic design approach of a low-power, high-speed pipelined ADC. The power consumptions of the capacitive digital to analog converter (DAC), two stage FinFET comparator with output inverter of the proposed ADC are lower than those of a conventional ADC. ADC is designed in 22 nm FinFET technology with medium sampling rate and 16-bit resolution are achieved.

Keywords

Analog to Digital Converter (ADC), Data Conversion, Low Power, Successive Approximation Register (SAR) Architecture, Digital to Analog Converter (DAC).

How to Cite this Article?

Reddy, M. C. S. (2021). Implementation of Pipelined ADC using 22 nm FinFET Technology. i-manager's Journal on Circuits and Systems, 9(2), 16-22. https://doi.org/10.26634/jcir.9.2.15094

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