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Power and Ground Bounce Reduction Techniques for Nanoscale VLSI Systems

M. Kavitha*

Department of Electronics and Communication Engineering, Government College of Engineering, Bargur, Tamilnadu, India.

Periodicity:July - December'2021
DOI : https://doi.org/10.26634/jcir.9.2.18473

Abstract

In the field of nanotechnology, leakage noise and ground reflections have become important considerations in the design of VLSI circuits. Power leakage is a serious problem, especially in handheld and portable battery powered devices, due to critical battery life. Ground bounce can cause false transactions, resulting in incorrect values in digital circuits. In nanoscale VLSIs, the problem of reducing leakage and ground bounce needs to be addressed in order to improve circuit performance. In this paper, two power gating techniques to minimize leakage and ground bounce are proposed. Leakage power and ground bounce noise are estimated for ISCAS'85 benchmark circuits and simulation results reveal that the proposed techniques mitigate maximum of 79% leakage power and 60% ground bounce than conventional techniques.

Keywords

Ground Bounce, ISCAS Benchmark Circuits, Leakage Power, Power Gating.

How to Cite this Article?

Kavitha, M. (2021). Power and Ground Bounce Reduction Techniques for Nanoscale VLSI Systems. i-manager's Journal on Circuits and Systems, 9(2), 1-8. https://doi.org/10.26634/jcir.9.2.18473

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