i-manager Publications

i-manager's Journal on Circuits and Systems (JCIR)

Current Issue Vol. 11 Issue 2

Voltage Stability and Power Loss Minimization with UPFC using Heuristic and Hybrid Heuristic Methods
Design and Analysis of Voltage Difference Transconductance Amplifier (VDTA) at FINFET CMOS Technology
Efficient Logic Cell Design for Ultralow-Energy Subthreshold Operation in Wearable Biomedical Systems
Design and Optimization of MSI-Enabled Multi-Precision Binary Multiplier Architecture
Analysis of Carbon Nanotube for Low Power Nano Electronics Applications

Most Cited

Volume 7 Issue 3 June - August 2019

Research Paper

Realization of Array Multiplier and Serial-Parallel Multiplier Architectures

Siripurapu Sridhar* , S. Rama Krishna**

*-** Lendi Institute of Engineering and Technology, Andhra Pradesh, India.

Sridhar, S., and Krishna, S. R. (2019). Realization of Array Multiplier and Serial-Parallel Multiplier Architectures. i-manager's Journal on Circuits and Systems , 7(3), 1-5. https://doi.org/10.26634/jcir.7.3.16834

Abstract

CMOS scaling relies on the device miniaturization and the interconnect dimensions to achieve high performance and curtails the escalating power-density. Since, multiplication algorithms and relevant high speed architectures extend significant contribution to the transient and dynamic power consumption of any system and thereby influence the total power consumption, multipliers of different bit-widths are deployed in signal and image Processing based VLSI applications ranging from processors to variety of application specific integrated circuits. On the other hand, Artificial Neural Networks (ANN) are well suitable for VLSI implementations because of their massive parallel structures comprised of processing Multiply Accumulate Carry (MAC) neuron elemental units. The proposed work focuses more on the design of variant bit Array Multiplier and Serial-Parallel Multiplier architectures targeting CMOS 130 nm technology. Both architectures are analyzed experimentally and relatively compared with rise-time, fall-time, power dissipation, delay parameters, etc.

References

[1]. Baugh, C. R., & Wooley, B. A. (1973). A two's complement parallel array multiplication algorithm. IEEE Transactions on Computers, 100(12), 1045-1047. https://doi.org/10.1109/T-C.1973.223648

[2]. Bewick, G. W. (1994). Fast multiplication: Algorithms and Implementation (Doctoral dissertation). Stanford University.

[3]. Cavanagh, J. J. F. (1984). Digital Computer Arithmetic: Design and Implementation. New York: McGraw-Hill.

[4]. Ciminiera, L., & Valenzano, A. (1988). Low cost serial multipliers for high-speed specialised processors. IEEE Proceedings E (Computers and Digital Techniques), 135(5), 259-265. https://doi.org/10.1049/ip-e.1988.0034

[5]. Egrioglu, E., Aladag, C. H., & Günay, S. (2008). A new model selection strategy in artificial neural networks. Applied Mathematics and Computation, 195(2), 591-597.

[6]. Holland, J. H. (1992). Adaptation in Natural and Artificial Systems: An introductory Analysis with Applications to Biology, Control, and Artificial Intelligence. MIT press.

[7]. Kim, S. M., Chung, J. G., & Parhi, K. K. (2002, May). Design of low error CSD fixed-width multiplier. In 2002 IEEE International Symposium on Circuits and Systems.(Vol. 1, pp. I-69). IEEE. https://doi.org/10.1109/ISCAS.2002.100977 9

[8]. Krizhevsky, A., Sutskever, I., & Hinton, G. E. (2012). Imagenet classification with deep convolutional neural networks. In Advances in Neural Information Processing Systems (pp. 1097-1105).

[9]. Mathew, K., Latha, S. A., Ravi, T., & Logashanmugam, E. (2013). Design and analysis of an array multiplier using an area efficient full adder cell in 32 nm CMOS technology. International Journal of Engineering and Science, 2(3), 8- 16.

[10]. Smith, S. G., & Denyer, P. B. (1988). Serial Data Computation. Boston, MA: Kluwer Academic Publisher.

[11]. Soniya, S. K. (2013). A review of different type of multipliers and multiplier-accumulator unit. International Journal of Emerging Trends & Technology in Computer Science (IJETTCS), 2(4), 364-368.

[12]. Sunder, S., El-Guibaly, F., & Antoniou, A. (1995). Two'scomplement fast serial-parallel multiplier. IEE Proceedings- Circuits, Devices and Systems, 142(1), 41-44. https://doi. org/10.1049/ip-cds:19951638.

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Research Paper

Area and Power Calculation of TSS LFSR and its Effect on Benchmark Circuits

Swati Agrawal* , Shanti Rathore**

*-** CV Raman University, Chhattisgarh, India.

Agarwal, S., and Rathore, S. (2019). Area and Power Calculation of TSS LFSR and its Effect on Benchmark Circuits. i-manager's Journal on Circuits and Systems , 7(3), 6-10. https://doi.org/10.26634/jcir.7.3.16979

Abstract

Linear Feedback Shift Registers (LFSRs) are basic building block of Built in Self-Test (BIST) circuits. Tri State Skip (TSS) method of pattern generation using LFSR is used in this research to form TSS LFSR and the results obtained for it are compared with other LFSRs, viz: pipelined LFSR, Gray LFSR, Binary Counter, and Gray Counter. The key objective of this paper is to calculate the area and power consumption of TSS LFSR. The results show that the power consumed by TSS LFSR is comparatively less than other LFSRS studied in comparison. Moreover, the number of gates used when using Transmission gates to design TSS LFSR is quite less than other LFSRs, thereby, minimizing area requirement.

References

[1]. Corno, E., Prinetto, P., Rebaudengo, M., & Reorda, M. S. (1998, April). A test pattern generation methodology for low th power consumption. In Proceedings 16 IEEE VLSI Test Symposium (pp. 453-457). IEEE. https://doi.org/10.1109/ VTEST.1998.670912

[2]. Goud, Y. S., & Madhavi, B. K. (2015). A novel block switch logic for state-skip test pattern generation in built in self test scheme. International Advanced Research Journal in Science, Engineering and Technology (ICRAESIT), 2(2), 40-45. https://doi.org/10.17148/IARJSET

[3]. Gunavathi, K., Paramasivam, K., Lavanya, P. S., & Umamageswaran, M. (2006, August). A novel BIST TPG for testing of VLSI circuits. In First International Conference on Industrial and Information Systems (pp. 109-114). IEEE. https://doi.org/10.1109/ICIIS.2006.365646

[4]. Hatami, S., Alisafaee, M., Atoofian, E., Navabi, Z., & Afzali-Kusha, A. (2005, May). A low-power scan-path architecture. In 2005 IEEE International Symposium on Circuits and Systems (pp. 5278-5281). IEEE. https://doi.org/ 10.1109/ISCAS.2005. 1465826

[5]. Nourani, M., Tehranipoor, M., & Ahmed, N. (2008). Lowtransition test pattern generation for BIST-based applications. IEEE Transactions on Computers, 57(3), 303-315. https://doi.org/10.1109/TC.2007.70794

[6]. Stroele, A. P., & Mayer, F. (1997, April). Methods to reduce test application time for accumulator-based self-test. In th Proceedings 15 IEEE VLSI Test Symposium (pp. 48-53). IEEE. https://doi.org/10.1109/ VTEST.1997.599440

[7]. Tenentes, V., Kavousianos, X., & Kalligeros, E. (2010). Single and variable-state-skip LFSRs: Bridging the gap between test data compression and test set embedding for IP cores. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29(10), 1640-1644. https://doi.org/10.1109/TCAD.2010.2051096

[8]. Voyiatzis, I. (2008). On embedding test patterns into lowpower BIST sequences. Journal of Computer Information Systems, 49(2), 58-64. https://doi.org/10.1080/0887 4417.2009.11646049

[9]. Whetsel, L. (2000, October). Adapting scan architectures for low power operation. In Proceedings International Test Conference 2000 (pp. 863-872). IEEE. https://doi.org/10.109/ TEST.2000.894297

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Research Paper

Designing the Optimized Energy of D-Flip Flop using Inverse Narrow Width with Pull Up/Down Network

Bandaru Sunil Kumar* , Dokinala Naga Sanjana, Inala Monisha, J. Sant Swaroop Satsangi, D.Venkatachari

*-***** Department of Electronics and Communication Engineering and Technology, JNTUK, Vizianagaram, Andhra Pradesh, India.

Kumar, B. S., Sanjana, D. N., Monisha, I., Satsangi, J. S. S., and Venkatachari, D. (2019). Designing the Optimized Energy of D-Flip Flop using Inverse Narrow Width with Pull Up/Down Network. i-manager's Journal on Circuits and Systems , 7(3), 11-16. https://doi.org/10.26634/jcir.7.3.16972

Abstract

Ultralow-energy consumption of electronic components has recommended the sub-threshold VLSI logic family in the development of standard CMOS circuits. This brief propounds an unbalanced pull-up or pull-down network together with an inverse narrow-width technique to increase the operating speed of the individual logic cells with respect to varying widths. Effective logical efforts will save both area and power in the process of device sizing and energy optimization. Experimentally, 16 tap - 8 bit finite IIR (Infinite Impulse Response) is optimized for the ultralow-energy concept and is fabricated under 0.13 µm CMOS Technology. We simulated the D-flip flop with 18 transistors with logic gates and implemented the D-flip flop with 10 transistor and 16 tap 8 bit (16 tap is 16 D-flip flop, 16 AND gates and 16 OR gates are used and 8 bit pattern is given). We implemented with 5 transistors and verified by the same procedure with 10 transistors and measured both power dissipation and delay for optimized power.

References

[1]. Akers, L. A. (1986). The inverse-narrow-width effect. IEEE Electron Device Letters, 7(7), 419-421. https://doi.org/ 10.1109/EDL.1986.26422

[2]. Alioto, M. (2010). Understanding DC behavior of subthreshold CMOS logic through closed-form analysis. IEEE Transactions on Circuits and Systems I: Regular Papers, 57(7), 1597-1607. https://doi.org/10.1109/TCSI.2009.2034 233

[3]. Calhoun, B. H., & Chandrakasan, A. (2004, August). Characterizing and modeling minimum energy operation for subthreshold circuits. In Proceedings of the 2004 International Symposium on Low Power Electronics and Design (pp. 90-95).

[4]. Chang, I. J., Park, S. P., & Roy, K. (2010). Exploring asynchronous design techniques for process-tolerant and energy-efficient subthreshold operation. IEEE Journal of Solid-State Circuits, 45(2), 401-410. https://doi.org/10.1 109/JSSC.2009.2036764

[5]. Frustaci, F., Corsonello, P., & Perri, S. (2012). Analytical delay model considering variability effects in subthreshold domain. IEEE Transactions on Circuits and Systems II: Express Briefs, 59(3), 168-172. https://doi.org/10.1109/ TCSII.2012.2184377

[6]. Hwang, M. E., Raychowdhury, A., Kim, K., & Roy, K. (2007, June). A 85mV 40nW process-tolerant subthreshold 8×8 FIR filter in 130nm technology. In 2007 IEEE Symposium on VLSI Circuits (pp. 154-155). IEEE. https://doi.org/10.1109/ VLSIC.2007.4342695

[7]. Kim, T. H., Keane, J., Eom, H., & Kim, C. H. (2007). Utilizing reverse short-channel effect for optimal subthreshold circuit design. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 15(7), 821-829. https://doi.org/10.1109/TVLSI.2007.899239

[8]. Klinefelter, A. M., Zhang, Y., Otis, B., & Calhoun, B. H. (2012). A programmable 34 nW/channel sub-threshold signal band power extractor on a body sensor node SoC. IEEE Transactions on Circuits and Systems II: Express Briefs, 59(12), 937-941. https://doi.org/10.1109/TCSII.2012.2231 041

[9]. Kwong, J., & Chandrakasan, A. P. (2006, October). Variation-driven device sizing for minimum energy subthreshold circuits. In Proceedings of the 2006 International Symposium on Low Power Electronics and Design (pp. 8- 13). https://doi.org/10.1145/1165573.1165578

[10]. Li, M. Z., Ieong, C. I., Law, M. K., Mak, P. I., Vai, M. I., & Martins, R. P. (2013, July). Sub-threshold standard cell library design for ultra-low power biomedical applications. In th 2013 35 Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC) (pp. 1454-1457). IEEE. https://doi.org/10.1109/EMBC.2013.6 609785

[11]. Liu, B., De Gyvez, J. P., & Ashouei, M. (2013). Subthreshold standard cell sizing methodology and library comparison. Journal of Low Power Electronics and Applications, 3(3), 233-249. https://doi.org/10.3390/jlpea 303233

[12]. Ma, W. H., Kao, J. C., Sathe, V. S., & Papaefthymiou, M. C. (2010). 187 MHz subthreshold-supply chargerecovery FIR. IEEE Journal of Solid-State Circuits, 45(4), 793- 803. https://doi.org/10.1109/JSSC.2010.2042247

[13]. Reynders, N., & Dehaene, W. (2012). Variation-resilient building blocks for ultra-low-energy sub-threshold design. IEEE Transactions on Circuits and Systems II: Express Briefs, 59(12), 898-902. https://doi.org/10.1109/TCSII2012.22310 22

[14]. Sutherland, I., Sproull, R. F., Sproull, B., & Harris, D. (1999). Logical Effort: Designing Fast CMOS Circuits. Morgan Kaufmann.

[15]. Tajalli, A., & Leblebici, Y. (2011). Design trade-offs in ultra-low-power digital nanoscale CMOS. IEEE Transactions on Circuits and Systems I: Regular Papers, 58(9), 2189- 2200. https://doi.org/10.1109/TCSI.2011.2112595

[16]. Wang, J. M., Fang, S. C., & Feng, W. S. (1994). New efficient designs for XOR and XNOR functions on the transistor level. IEEE Journal of Solid-State Circuits, 29(7), 780-786. https://doi.org/10.1109/4.303715

[17]. Zhang, F., Mishra, A., Richardson, A. G., Zanos, S., & Otis, B. P. (2010, September). A low-power multi-band ECoG/EEG interface IC. In IEEE Custom Integrated Circuits Conference 2010 (pp. 1-4). IEEE. https://doi.org/ 10.1109/CICC.2010.5617607

[18]. Zhou, J., Jayapal, S., Busze, B., Huang, L., & Stuyt, J. (2012). A 40 nm dual-width standard cell library for near/sub-threshold operation. IEEE Transactions on Circuits and Systems I: Regular Papers, 59(11), 2569-2577. https://doi.org/10.1109/TCSI.2012.2190674

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Research Paper

130 Nm CMOS Technology based Baugh-Wooley and Wallace-Tree-Multiplier Architectures

Siripurapu Sridhar* , Hima Bindhu, Paxani P.*

*-*** Lendi Institute of Engineering and Technology, Andhra Pradesh, India.

Sridar, S., Bindhu, H., and Paxani P. (2019). 130 Nm CMOS Technology based Baugh-Wooley and Wallace-Tree-Multiplier Architectures. i-manager's Journal on Circuits and Systems , 7(3), 17-25. https://doi.org/10.26634/jcir.7.3.16455

Abstract

The enhanced usage of multiplier circuits in various applications has prompted researchers to evolve high-speed and power optimized multiplier design architectures. Subsequently, power management optimizations as well as high speed designs are of greatest concern today, especially while working with digital signal processors, and other audio- video image processing circuits utilizing artificial neural networks. This work mainly focuses on providing efficient and optimized CMOS designs for 2-bit, 4-bit Wallace Tree Multiplier and Baugh-Wooley Multiplier architectures for applications in advanced filter designs comprised of simple to complex adders' circuits. The proposed architectures are verified experimentally using Mentor Graphics tools targeting the 130 nm technology design parameters. Design architectures are comparatively verified with relevant parameters like rise-time, fall-time, path delay, power dissipation, silicon area, etc. Both the architectures display few tradeoffs between power dissipation and delay parameters. Analysis with the implementation of proposed architectures for usage in Multipliers and Accumulate Carry (MAC) unit and other processing unit blocks are performed for further implementations.

References

[1]. Alaoui, C. (2011). Design and simulation of a modified architecture of carry save adder. International Journal of Engineering (IJE), 5(1), 102-113.

[2]. Amanollahi, S., & Jaberipur, G. (2017). Fast energy efficient radix-16 sequential multiplier. IEEE Embedded Systems Letters, 9(3), 73-76. https://doi.org/10.1109/LES. 2017.2714259

[3]. Antelo, E., Montuschi, P., & Nannarelli, A. (2016). Improved 64-bit radix-16 Booth multiplier based on partial product array height reduction. IEEE Transactions on Circuits and Systems I: Regular Papers, 64(2), 409-418. https://doi.org/10.1109/TCSI.2016.2561518

[4]. Anuar, N., Takahashi, Y., & Sekine, T. (2010). Two phase clocked adiabatic static CMOS logic and its logic family. JSTS: Journal of Semiconductor Technology and Science, 10(1), 1-10.

[5]. Bewick, G. W. (1994). Fast multiplication: Algorithms and implementation (Doctoral dissertation), Stanford University.

[6]. Chandel, D., Kumawat, G., Lahoty, P., Chandrodaya, V. V., & Sharma, S. (2013). Booth multiplier: Ease of multiplication. International Journal of Emerging Technology and Advanced Engineering, 3(3), 118-122.

[7]. Karthikeyan, A., Sumathi, K., Nivash, V. S., Logeshwaran, K., & Rajkumar, R. P. (2018). An efficient VLSI implementation 32-bit Baugh-Wooley multiplier. International Journal of Creative Research Thoughts (IJCRT), 6(1), 802-805.

[8]. Kuang, S. R., Wang, J. P., & Guo, C. Y. (2009). Modified booth multipliers with a regular partial product array. IEEE Transactions on Circuits and Systems II: Express Briefs, 56(5), 404-408. https://doi.org/10.1109/TCSII.2009.2019334

[9]. Kumawat, P. K., & Sujediya, G. (2017). Optimize circuit and compare of 8 x 8 wallace Tree Multiplier using GDI and CMOS technology. International Journal of Advanced Engineering Research and Science, 4, 20-24. https://doi.org/10.22161/ijaers.4.7.3.

[10]. Mathew, K., Latha, S. A., Ravi, T., & Logashanmugam, E. (2013). Design and analysis of an array multiplier using an area efficient full adder cell in 32 nm CMOS technology. International Journal of Engineering and Science, 2(3), 8- 16.

[11]. Moss, D. J., Boland, D., & Leong, P. H. (2018). A twospeed, radix-4, serial–parallel multiplier. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27(4), 769- 777. https://doi.org/10.1109/TVLSI.2018.2883645

[12]. Qiqieh, I., Shafik, R., Tarawneh, G., Sokolov, D., Das, S., & Yakovlev, A. (2018). Significance-driven logic compression for energy-efficient multiplier design. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 8(3), 417-430. https://doi.org/10.1109/ JETCAS.2018.2846410

[13]. Tang, G. M., Takagi, K., & Takagi, N. (2017). 32× 32-bit 4-bit bit-slice integer multiplier for RSFQ microprocessors. IEEE Transactions on Applied Superconductivity, 27(3), 1-5. https://doi.org/10.1109/TASC.2017.2662700

[14]. Tiwari, G. (2013). Analysis, verification and FPGA implementation of low power multiplier. International Journal of Research in Engineering and Technology (IJRET), 2(3), 220 - 224.

[15]. Yengade, K. S. N., & Indurkar, P. R. (2017). Design of low power Baugh-Wooley multiplier. International Journal for Research in Applied Science & Engineering Technology (IJRASET), 5(7), 813-817.

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Research Paper

A Survey on Various Generations and Different Applications of Current Conveyors

G. Appala Naidu* , B. Tirumala Krishna**

* Department of Electronics and Communication Engineering, University College of Engineering, Vizianagaram, JNTUK, India.

** Department of Electronics and Communication Engineering, Jawaharlal Nehru Technological University, Kakinada Andhra Pradesh India.

Naidu, G. A., and Krishna, B. T. (2019). A Survey on Various Generations and Different Applications of Current Conveyors. i-manager's Journal on Circuits and Systems , 7(3), 26-38. https://doi.org/10.26634/jcir.7.3.16648

Abstract

Many electronic systems use active devices like operational amplifiers, operational transconductance amplifier (OTA) that use voltage mode of operations, which have their own advantages and disadvantages. Now-a-days, the current mode of operation plays an important role compared to the voltage mode of operation. In this paper, surveys on various generations of the current conveyors are conducted. From this present study, it has been observed that second generation current conveyor is the most widely used one. The mathematical analysis of the second-generation current conveyors is performed. The simulation results are carried out using Multisim Software. It has been observed that using second generation current conveyors, low power applications can be designed. Some of the applications of the current conveyor are explained with illustrations.

References

[1]. Smith, K. C., and Sedra, A. S. (1968). The current conveyor-a new circuit building block. IEEE Proceeding on Circuits and Systems, 56 (8), 1368 -1369.

[2]. Sedra, A. S. and Smith, K. C. (1970). A second generation current conveyor and its application. IEEE Transaction on Circuit Theory, 17(1), 132-134.

[3]. Newcomb R W. (1968). Active Integrated Network Synthesis. Englewood Cliffs, NJ: Prentice-Hall.

[4]. Cha, H. W., and Watanabe, K (1996). Wide band CMOS current conveyor. Electronics Letters, 32(14), 1245- 1246.

[5]. Kasemsuwan, V. and Nakhlo, W. (2007). A simple 1.5 V rail-to-rail CMOS current conveyor, Journal of Circuits, Systems, and Computers., 16(4), 627-639.

[6]. Sobhy, E. A., and Soliman, A. M (2010). Realizations of fully differential voltage second-generation current conveyor with an application, International Journal of Circuit Theory and Applications, 38(1), 441-452.

[7]. Ismail, A. M., and Soliman, A. M. (1998). Wideband CMOS current conveyor, Electron Letter, 34(25),.2368–236 9.

[8]. Li, Y. A (2015). Derivation for current-mode Wien oscillators exploitation CCCCTAs, Analog Integrated Circuits Signal method., 84 (3), 479–490.

[9]. Li, Y. A (2014). Electronically tunable current-mode biquadratic filter and four phase construction oscillator', Microelectronics Journal, 45 (3), 330–335.

[10]. Biolek, D., Lahiri, A., Jaikla, W., et al. (2011). Realization of electronically tunable voltagemode/ current-mode construction curving generator exploitation ZC-CGCDBA, Microelectronics Journal, 42 (10),1116–1123.

[11]. Jerabek, J., Sotner, R., Vrba, K. (2014). Tunable polyphase generator exploitation diamond transistors with voltage controlled condition of oscillation for amplitude stabilization, Elektron Elektrotech., 20(1), 45–48.

[12]. Li, Y. A (2018). RC oscillators supported high-Q frequency choosing network , IET Circuits Devices System, Vol. 12 (1), 82-87.

i-manager's Journal on Circuits and Systems (JCIR)

Current Issue Vol. 11 Issue 2

Most Read

Most Cited

Volume 7 Issue 3 June - August 2019

Realization of Array Multiplier and Serial-Parallel Multiplier Architectures

Siripurapu Sridhar* , S. Rama Krishna**

*-** Lendi Institute of Engineering and Technology, Andhra Pradesh, India.

Sridhar, S., and Krishna, S. R. (2019). Realization of Array Multiplier and Serial-Parallel Multiplier Architectures. i-manager's Journal on Circuits and Systems , 7(3), 1-5. https://doi.org/10.26634/jcir.7.3.16834

Abstract

References

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Area and Power Calculation of TSS LFSR and its Effect on Benchmark Circuits

Swati Agrawal* , Shanti Rathore**

*-** CV Raman University, Chhattisgarh, India.

Agarwal, S., and Rathore, S. (2019). Area and Power Calculation of TSS LFSR and its Effect on Benchmark Circuits. i-manager's Journal on Circuits and Systems , 7(3), 6-10. https://doi.org/10.26634/jcir.7.3.16979

Abstract

References

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Designing the Optimized Energy of D-Flip Flop using Inverse Narrow Width with Pull Up/Down Network

Bandaru Sunil Kumar* , Dokinala Naga Sanjana**, Inala Monisha***, J. Sant Swaroop Satsangi****, D.Venkatachari*****

*-***** Department of Electronics and Communication Engineering and Technology, JNTUK, Vizianagaram, Andhra Pradesh, India.

Kumar, B. S., Sanjana, D. N., Monisha, I., Satsangi, J. S. S., and Venkatachari, D. (2019). Designing the Optimized Energy of D-Flip Flop using Inverse Narrow Width with Pull Up/Down Network. i-manager's Journal on Circuits and Systems , 7(3), 11-16. https://doi.org/10.26634/jcir.7.3.16972

Abstract

References

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130 Nm CMOS Technology based Baugh-Wooley and Wallace-Tree-Multiplier Architectures

Siripurapu Sridhar* , Hima Bindhu**, Paxani P.***

*-*** Lendi Institute of Engineering and Technology, Andhra Pradesh, India.

Sridar, S., Bindhu, H., and Paxani P. (2019). 130 Nm CMOS Technology based Baugh-Wooley and Wallace-Tree-Multiplier Architectures. i-manager's Journal on Circuits and Systems , 7(3), 17-25. https://doi.org/10.26634/jcir.7.3.16455

Abstract

References

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A Survey on Various Generations and Different Applications of Current Conveyors

G. Appala Naidu* , B. Tirumala Krishna**

* Department of Electronics and Communication Engineering, University College of Engineering, Vizianagaram, JNTUK, India. ** Department of Electronics and Communication Engineering, Jawaharlal Nehru Technological University, Kakinada Andhra Pradesh India.

Naidu, G. A., and Krishna, B. T. (2019). A Survey on Various Generations and Different Applications of Current Conveyors. i-manager's Journal on Circuits and Systems , 7(3), 26-38. https://doi.org/10.26634/jcir.7.3.16648

Abstract

References

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Bandaru Sunil Kumar* , Dokinala Naga Sanjana, Inala Monisha, J. Sant Swaroop Satsangi, D.Venkatachari

Siripurapu Sridhar* , Hima Bindhu, Paxani P.*

* Department of Electronics and Communication Engineering, University College of Engineering, Vizianagaram, JNTUK, India.

** Department of Electronics and Communication Engineering, Jawaharlal Nehru Technological University, Kakinada Andhra Pradesh India.