Loss Distribution Methodology with a Sense Of Emission Dispatch
Low Power Optimization Technique Based Linear Feedback Shift Register
Leakage Power Reduction Using Multi Modal Driven Hierarchical Power Mode Switches
Validation of IOV chain using OVM Technique
Performance of Continuous and Discontinuous Space Vector Pwm Technique for Open End Winding Induction Motor Drive
Electronic Circuit Design for Electromagnetic Compliance through Problem-Based Learning
Trioinformatics: The Innovative and Novel Logic Notation That Defines, Explains, and Expresses the Rational Application of The Law of Trichotomy for Digital Instrumentation and Circuit Design
Design Of a Novel Gated 5T SRAM Cell with Low Power Dissipation in Active and Sleep Mode
A Two Stage Power Optimized Implantable Neural Amplifier Based on Cascoded Structures
An Efficient Hybrid PFSCL based Implementation of Asynchronous Pipeline
CMOS scaling relies on the device miniaturization and the interconnect dimensions to achieve high performance and curtails the escalating power-density. Since, multiplication algorithms and relevant high speed architectures extend significant contribution to the transient and dynamic power consumption of any system and thereby influence the total power consumption, multipliers of different bit-widths are deployed in signal and image Processing based VLSI applications ranging from processors to variety of application specific integrated circuits. On the other hand, Artificial Neural Networks (ANN) are well suitable for VLSI implementations because of their massive parallel structures comprised of processing Multiply Accumulate Carry (MAC) neuron elemental units. The proposed work focuses more on the design of variant bit Array Multiplier and Serial-Parallel Multiplier architectures targeting CMOS 130 nm technology. Both architectures are analyzed experimentally and relatively compared with rise-time, fall-time, power dissipation, delay parameters, etc.
Linear Feedback Shift Registers (LFSRs) are basic building block of Built in Self-Test (BIST) circuits. Tri State Skip (TSS) method of pattern generation using LFSR is used in this research to form TSS LFSR and the results obtained for it are compared with other LFSRs, viz: pipelined LFSR, Gray LFSR, Binary Counter, and Gray Counter. The key objective of this paper is to calculate the area and power consumption of TSS LFSR. The results show that the power consumed by TSS LFSR is comparatively less than other LFSRS studied in comparison. Moreover, the number of gates used when using Transmission gates to design TSS LFSR is quite less than other LFSRs, thereby, minimizing area requirement.
Ultralow-energy consumption of electronic components has recommended the sub-threshold VLSI logic family in the development of standard CMOS circuits. This brief propounds an unbalanced pull-up or pull-down network together with an inverse narrow-width technique to increase the operating speed of the individual logic cells with respect to varying widths. Effective logical efforts will save both area and power in the process of device sizing and energy optimization. Experimentally, 16 tap - 8 bit finite IIR (Infinite Impulse Response) is optimized for the ultralow-energy concept and is fabricated under 0.13 µm CMOS Technology. We simulated the D-flip flop with 18 transistors with logic gates and implemented the D-flip flop with 10 transistor and 16 tap 8 bit (16 tap is 16 D-flip flop, 16 AND gates and 16 OR gates are used and 8 bit pattern is given). We implemented with 5 transistors and verified by the same procedure with 10 transistors and measured both power dissipation and delay for optimized power.
The enhanced usage of multiplier circuits in various applications has prompted researchers to evolve high-speed and power optimized multiplier design architectures. Subsequently, power management optimizations as well as high speed designs are of greatest concern today, especially while working with digital signal processors, and other audio- video image processing circuits utilizing artificial neural networks. This work mainly focuses on providing efficient and optimized CMOS designs for 2-bit, 4-bit Wallace Tree Multiplier and Baugh-Wooley Multiplier architectures for applications in advanced filter designs comprised of simple to complex adders' circuits. The proposed architectures are verified experimentally using Mentor Graphics tools targeting the 130 nm technology design parameters. Design architectures are comparatively verified with relevant parameters like rise-time, fall-time, path delay, power dissipation, silicon area, etc. Both the architectures display few tradeoffs between power dissipation and delay parameters. Analysis with the implementation of proposed architectures for usage in Multipliers and Accumulate Carry (MAC) unit and other processing unit blocks are performed for further implementations.
Many electronic systems use active devices like operational amplifiers, operational transconductance amplifier (OTA) that use voltage mode of operations, which have their own advantages and disadvantages. Now-a-days, the current mode of operation plays an important role compared to the voltage mode of operation. In this paper, surveys on various generations of the current conveyors are conducted. From this present study, it has been observed that second generation current conveyor is the most widely used one. The mathematical analysis of the second-generation current conveyors is performed. The simulation results are carried out using Multisim Software. It has been observed that using second generation current conveyors, low power applications can be designed. Some of the applications of the current conveyor are explained with illustrations.
