Area and Power Calculation of TSS LFSR and its Effect on Benchmark Circuits

Swati Agrawal*, Shanti Rathore**
*-** CV Raman University, Chhattisgarh, India.
Periodicity:June - August'2019
DOI : https://doi.org/10.26634/jcir.7.3.16979

Abstract

Linear Feedback Shift Registers (LFSRs) are basic building block of Built in Self-Test (BIST) circuits. Tri State Skip (TSS) method of pattern generation using LFSR is used in this research to form TSS LFSR and the results obtained for it are compared with other LFSRs, viz: pipelined LFSR, Gray LFSR, Binary Counter, and Gray Counter. The key objective of this paper is to calculate the area and power consumption of TSS LFSR. The results show that the power consumed by TSS LFSR is comparatively less than other LFSRS studied in comparison. Moreover, the number of gates used when using Transmission gates to design TSS LFSR is quite less than other LFSRs, thereby, minimizing area requirement.

Keywords

Linear Feedback Shift Registers (LFSR), Built-in Self Test (BIST), Tri State Skip (TSS), Test Pattern Generators (TPG), Circuit Under Test (CUT), System on Chip (SoC).

How to Cite this Article?

Agarwal, S., and Rathore, S. (2019). Area and Power Calculation of TSS LFSR and its Effect on Benchmark Circuits. i-manager's Journal on Circuits and Systems , 7(3), 6-10. https://doi.org/10.26634/jcir.7.3.16979

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