References
[1]. Corno, E., Prinetto, P., Rebaudengo, M., & Reorda, M. S.
(1998, April). A test pattern generation methodology for low
th power consumption. In Proceedings 16 IEEE VLSI Test
Symposium (pp. 453-457). IEEE. https://doi.org/10.1109/
VTEST.1998.670912
[2]. Goud, Y. S., & Madhavi, B. K. (2015). A novel block switch
logic for state-skip test pattern generation in built in self test
scheme. International Advanced Research Journal in
Science, Engineering and Technology (ICRAESIT), 2(2), 40-45.
https://doi.org/10.17148/IARJSET
[3]. Gunavathi, K., Paramasivam, K., Lavanya, P. S., &
Umamageswaran, M. (2006, August). A novel BIST TPG for
testing of VLSI circuits. In First International Conference on
Industrial and Information Systems (pp. 109-114). IEEE.
https://doi.org/10.1109/ICIIS.2006.365646
[4]. Hatami, S., Alisafaee, M., Atoofian, E., Navabi, Z., &
Afzali-Kusha, A. (2005, May). A low-power scan-path
architecture. In 2005 IEEE International Symposium on
Circuits and Systems (pp. 5278-5281). IEEE. https://doi.org/
10.1109/ISCAS.2005. 1465826
[5]. Nourani, M., Tehranipoor, M., & Ahmed, N. (2008). Lowtransition
test pattern generation for BIST-based applications.
IEEE Transactions on Computers, 57(3), 303-315.
https://doi.org/10.1109/TC.2007.70794
[6]. Stroele, A. P., & Mayer, F. (1997, April). Methods to reduce
test application time for accumulator-based self-test. In
th Proceedings 15 IEEE VLSI Test Symposium (pp. 48-53). IEEE.
https://doi.org/10.1109/ VTEST.1997.599440
[7]. Tenentes, V., Kavousianos, X., & Kalligeros, E. (2010).
Single and variable-state-skip LFSRs: Bridging the gap
between test data compression and test set embedding for
IP cores. IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems, 29(10), 1640-1644.
https://doi.org/10.1109/TCAD.2010.2051096
[8]. Voyiatzis, I. (2008). On embedding test patterns into lowpower
BIST sequences. Journal of Computer Information
Systems, 49(2), 58-64. https://doi.org/10.1080/0887
4417.2009.11646049
[9]. Whetsel, L. (2000, October). Adapting scan architectures
for low power operation. In Proceedings International Test
Conference 2000 (pp. 863-872). IEEE. https://doi.org/10.109/
TEST.2000.894297