References
[1]. Alaoui, C. (2011). Design and simulation of a modified
architecture of carry save adder. International Journal of
Engineering (IJE), 5(1), 102-113.
[2]. Amanollahi, S., & Jaberipur, G. (2017). Fast energy
efficient radix-16 sequential multiplier. IEEE Embedded
Systems Letters, 9(3), 73-76. https://doi.org/10.1109/LES.
2017.2714259
[3]. Antelo, E., Montuschi, P., & Nannarelli, A. (2016).
Improved 64-bit radix-16 Booth multiplier based on partial
product array height reduction. IEEE Transactions on Circuits
and Systems I: Regular Papers, 64(2), 409-418.
https://doi.org/10.1109/TCSI.2016.2561518
[4]. Anuar, N., Takahashi, Y., & Sekine, T. (2010). Two phase
clocked adiabatic static CMOS logic and its logic family.
JSTS: Journal of Semiconductor Technology and Science,
10(1), 1-10.
[5]. Bewick, G. W. (1994). Fast multiplication: Algorithms and
implementation (Doctoral dissertation), Stanford University.
[6]. Chandel, D., Kumawat, G., Lahoty, P., Chandrodaya, V.
V., & Sharma, S. (2013). Booth multiplier: Ease of
multiplication. International Journal of Emerging Technology
and Advanced Engineering, 3(3), 118-122.
[7]. Karthikeyan, A., Sumathi, K., Nivash, V. S., Logeshwaran,
K., & Rajkumar, R. P. (2018). An efficient VLSI implementation
32-bit Baugh-Wooley multiplier. International Journal of
Creative Research Thoughts (IJCRT), 6(1), 802-805.
[8]. Kuang, S. R., Wang, J. P., & Guo, C. Y. (2009). Modified
booth multipliers with a regular partial product array. IEEE
Transactions on Circuits and Systems II: Express Briefs, 56(5),
404-408. https://doi.org/10.1109/TCSII.2009.2019334
[9]. Kumawat, P. K., & Sujediya, G. (2017). Optimize circuit
and compare of 8 x 8 wallace Tree Multiplier using GDI and CMOS technology. International Journal of Advanced Engineering Research and Science, 4, 20-24. https://doi.org/10.22161/ijaers.4.7.3.
[10]. Mathew, K., Latha, S. A., Ravi, T., & Logashanmugam,
E. (2013). Design and analysis of an array multiplier using an
area efficient full adder cell in 32 nm CMOS technology.
International Journal of Engineering and Science, 2(3), 8-
16.
[11]. Moss, D. J., Boland, D., & Leong, P. H. (2018). A twospeed,
radix-4, serial–parallel multiplier. IEEE Transactions
on Very Large Scale Integration (VLSI) Systems, 27(4), 769-
777. https://doi.org/10.1109/TVLSI.2018.2883645
[12]. Qiqieh, I., Shafik, R., Tarawneh, G., Sokolov, D., Das,
S., & Yakovlev, A. (2018). Significance-driven logic
compression for energy-efficient multiplier design. IEEE
Journal on Emerging and Selected Topics in Circuits and
Systems, 8(3), 417-430. https://doi.org/10.1109/
JETCAS.2018.2846410
[13]. Tang, G. M., Takagi, K., & Takagi, N. (2017). 32× 32-bit
4-bit bit-slice integer multiplier for RSFQ microprocessors.
IEEE Transactions on Applied Superconductivity, 27(3), 1-5.
https://doi.org/10.1109/TASC.2017.2662700
[14]. Tiwari, G. (2013). Analysis, verification and FPGA
implementation of low power multiplier. International
Journal of Research in Engineering and Technology (IJRET),
2(3), 220 - 224.
[15]. Yengade, K. S. N., & Indurkar, P. R. (2017). Design of
low power Baugh-Wooley multiplier. International Journal
for Research in Applied Science & Engineering Technology
(IJRASET), 5(7), 813-817.