Designing the Optimized Energy of D-Flip Flop using Inverse Narrow Width with Pull Up/Down Network

Bandaru Sunil Kumar*, Dokinala Naga Sanjana**, Inala Monisha***, J. Sant Swaroop Satsangi****, D.Venkatachari*****
*-***** Department of Electronics and Communication Engineering and Technology, JNTUK, Vizianagaram, Andhra Pradesh, India.
Periodicity:June - August'2019
DOI : https://doi.org/10.26634/jcir.7.3.16972

Abstract

Ultralow-energy consumption of electronic components has recommended the sub-threshold VLSI logic family in the development of standard CMOS circuits. This brief propounds an unbalanced pull-up or pull-down network together with an inverse narrow-width technique to increase the operating speed of the individual logic cells with respect to varying widths. Effective logical efforts will save both area and power in the process of device sizing and energy optimization. Experimentally, 16 tap - 8 bit finite IIR (Infinite Impulse Response) is optimized for the ultralow-energy concept and is fabricated under 0.13 µm CMOS Technology. We simulated the D-flip flop with 18 transistors with logic gates and implemented the D-flip flop with 10 transistor and 16 tap 8 bit (16 tap is 16 D-flip flop, 16 AND gates and 16 OR gates are used and 8 bit pattern is given). We implemented with 5 transistors and verified by the same procedure with 10 transistors and measured both power dissipation and delay for optimized power.

Keywords

CMOS, Device Sizing, Finite Impulse Response (FIR) Realization, Inverse Narrow Width (INW), Ultralow Energy, Ultralow Voltage.

How to Cite this Article?

Kumar, B. S., Sanjana, D. N., Monisha, I., Satsangi, J. S. S., and Venkatachari, D. (2019). Designing the Optimized Energy of D-Flip Flop using Inverse Narrow Width with Pull Up/Down Network. i-manager's Journal on Circuits and Systems , 7(3), 11-16. https://doi.org/10.26634/jcir.7.3.16972

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