Development of a 4-Digit BCD Multiplier Architecture with Similarity Investigator
A Compact Plus Shaped with L-Shaped Slotted Microstrip Patch Antenna for GSM, WLAN, WiMAX, C- and X- Band Applications
Vaccination Identification System using Raspberry Pi
A Compact Wideband Monopole Antenna with DGS for WiMAX/WLAN/5G Applications
Analysis of Carbon Nanotube for Low Power Nano Electronics Applications
The Impact of Substrate Doping Concentration on Electrical Characteristics of 45nm Nmos Device
A Study on Globally Asynchronous and locally Synchronous System
Performance Analysis of Modified Source Junctionless Fully Depleted Silicon-on-Insulator MOSFET
Method of 2.5 V RGMII Interface I/O Duty Cycle and Delay Skew Enhancement
Automatic Accident Detection and Tracking of Vehicles by Using MEMS
Efficient Image Compression Algorithms Using Evolved Wavelets
Computer Modeling and Simulation of Ultrasonic Signal Processing and Measurements
Effect of Nano-Coatings on Waste-to-Energy (WTE) plant : A Review
ANFIS Controlled Solar Pumping System
Smart Agricultural Monitoring and Irrigation System using IoT
In this paper, the authors present a comparison through a simulation study, among different hetero structure devices, like Metal Semiconductor Field Effect Transistor (MESFET), High Electron Mobility Transistor (HEMT), and Tunnel Field Effect Transistor (TFET), with reference to their applications in electronic field. In particular, MESFET and HEMT present good performance in power amplifiers and they are characterized by high mobility of the charge carriers that allows to consume less at high frequency. TFET is the newest experimental device, which has a very powerful application in logic circuits, ultra low-power specific analog ICs with better temperature strength and low-power SRAM.
The authors have developed a combined approach to reduce the effect of noise from the medical images. Noises are generally originated due to physical processes of imaging rather than in the tissue textures. Various types of noise signals, viz. photon, electronics, quantization, etc., often contribute to degrade the image quality. In general, the overall noise is assumed to be additive with a zero-mean, constant-variance Gaussian distribution, which is commonly known as Additive White Gaussian Noise (AWGN). In this paper, de-noising methods are applied on Computed Tomography (CT) images using a proposed combined method which combines bivariate thresholding and enhanced total variation methods using wavelet based image fusion technique. This method provides better results in terms of Peak Signal to Noise Ratio (PSNR).
In this paper, an efficient Dual power supply Static Random Access Memory (SRAM) is designed which reduces power consumption in Active and Standby mode. To achieve this, different circuit techniques is introduced to minimize both power modes particularly at room temperature. If the circuit operates in Active mode, a Bit Line (BL) power calculator is used uniformly to set the supply voltages between the cells or nets. In the stand-by mode, a digitally controllable retention circuit is used to regulate the supply voltages with small control power. Efficient circuit techniques of SRAM reveal the power reduction of 27% in Active mode and 85% in Stand-by mode. The design is carried out in Code Composer Studio (CCS) as the software environment and MSP430G2553 is the target Hardware device. When compared with the conventional schemes, the proposed design reduces power consumption at a greater extent.
Design and implementation of memory devices are becoming a challenge for the memory designers due to various limitations. Leakage power dissipation and low data stability are the main constraints, while designing memory integrated circuits. In this paper, a new 8T Static Random Access Memory (SRAM) cell, that adopts a single bit line scheme has been proposed to limit the leakage current as well as to gain high data stability. The proposed circuit consumes 671.22 pA leakage current during idle state of the circuit. It shows the high data stability 343 MV and 329 MV during read and hold state, respectively. Additionally, this paper contains 64-bit memory unit of the proposed 8T SRAM cell (8 x 8) array. The array comprises of row decoder, column decoder, and sense amplifier. The proposed 8T SRAM cell is 16.45X and 43.78X fast during read 0 and read 1 operations, respectively, while during write 0 and write 1 operations the delay is reduced up to 8.05% and 8.46%, respectively when compared with (8 x 8) array of 6T SRAM cell. During read 0 and read 1, it is fast by 16.45X and 43.78X, respectively. The average power consumption during read 1/0 and write 1/0 operations are 99.5% /60.05% and 99.61% /59.82% less as compare to 6T SRAM array, respectively.
This paper proposes the analysis of various parameters after simulations of Photonic crystal fibers having air holes arranged in octagonal shape. Some of the air-holes replaced by some other liquid of refractive index differ from air to achieve more effective responses. This Octagonal Photonic Crystal Fiber (O-PCF) consists of four rings in which the air holes are placed. Four holes in the innermost ring of O-PCF are filled with Ethanol instead of air. The parameter calculations are done by varying the hole diameters, pitch values, and wavelengths while keeping the perfectly matched layer (PML) values constant. COMSOL Multiphysics is the software platform used to design these proposed structures, which uses Finite Element Method (FEM). The calculation of confinement loss and graphical representation are done in MATLAB. The advantage of taking ethanol as a substitute of air is that the confinement loss is reduced as compared to the confinement loss with only air hole PCF structures.
Driven by Moore's law, the scaling of devices has reached nanoscale. The journey of miniaturizations has encountered several challenges to attain desired electrical characteristics to meet the demand in the era of information technology. A Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device, being a major building block for designing both analog and digital circuits in IC design technology, has consequently undergone multiple structural variations to meet these challenges.
Planar as well as SOI multi-gate MOSFET devices are the front runners, amongst them. These devices have better controlling ability due to inherent advantage of multi-gate technology. This paper, carries out an analysis of an improved Fin Field Effect Transistor (FinFET) device designed for 16 nm channel length. Its performance metrics are compared with a regular design. A 16 nm FinFET design using nitride layers is implemented using Technology Computer Aided Design (TCAD) and analysis of threshold voltage, transconductance, Subthreshold Slope (SS), leakage current, charge density variations along fin, quasi Fermi Energy variations of electrons, electron net electron charge, carrier recombination, and mobility along the channel and an ability to withstand temperature is carried out. Timing analysis is also carried out implementing a resistive load inverter employing both the devices. The results are analyzed and compared with simple planar counterpart along with justification claiming the improved spacer FINFET design along with its limitations.