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i-manager's Journal on Electronics Engineering (JELE)

Current Issue Vol. 15 Issue 1

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Volume 6 Issue 2 December - February 2016 [Open Access]

Article

RFID Technology for Biomedical Applications: State of Art and Future Developments

Roberto Marani* , 0**

* Researcher, Consiglio Nazionale Delle Ricerche, Istituto di Studi sui Sistemi Intelligenti per l'Automazione (ISSIA), Bari, Italy.

** Full Professor, Electronics and Head of Electronic Devices Laboratory, Department of Electrical and Information Engineering, Polytechnic University of Bari, Italy.

Marani, R., and Perri, A.G. (2016). RFID Technology for Biomedical Applications: State of Art and Future Developments. i-manager's Journal on Electronics Engineering, 6(2), 1-12. https://doi.org/10.26634/jele.6.2.3761

Abstract

In this paper some of the possible applications in the biomedical field of the RFID technology are presented, giving an idea of the wide range of advantages that RFID devices are able to provide. In particular, those aspects of RFID technology were examined, which make possible the realization of miniaturized devices, implantable in the human body and powered from the outside, and can monitor the biological functions of individuals or even enable the therapy of diseases. Moreover, some aspects that need to be improved in the future research works are discussed such as the biocompatibility of the material for the implantable devices, the long-term exposure of the human body to electromagnetic fields, the interference caused by surrounding metallic parts, the attenuation of RF signals at particularly high frequency values and the implementation of a safe communication channel in order to guarantee the privacy of the individual.

References

[1]. Talone P. and Russo G., (2007). “RFID, Fondamenti diuna tecnologia silenziosamente pervasiva”. Fondazione Ugo Bordoni, Rome, Italy, pp. 1-445.

[2]. H. Aubert H., (2011). “RFID Technology for Human Implant Devices, Comptes rendus à l'Académie des Sciences”. Special issue on Nanosciences/nanotechn ologies, pp. 1-18.

[3]. Jensen K., Weldon J., Garcia H. and Zettl A., (2007). “Nanotube radio”. Nano Letters, Vol. 7, No.11, pp. 3508- 3511.

[4]. Sauer C., Stanacevic M., Cauwenberghs G., and Thakor N. (2005). “Power harvesting and telemetry in CMOS for implanted devices”. IEEE Transactions on Circuits and Systems, Vol. 52, No.12, pp 2605-2613.

[5]. Freudenthal E., Herrera D., Kautz F., Natividad C., Ogrey A., Sipla J., Sosa A., Betancourt C., and Estevez L., (2007). “Evaluation Of HF RFID for Implanted Medical Applications”. Departmental Technical Reports (CS), Paper 162.

[6]. McCreery D. et al., (2006). “Microelectrode array for chronic deep-brain microstimulation and recording”. IEEE Transactions on Biomedical Engineering, Vol. 53, No. 4, pp. 726-737.

[7]. Chen M. et al., (2011). “Body Area Networks: A Survey”. ACM/Springer Mobile Networks and Applications (MONET).

[8]. Hamad-Schifferli K. et al., (2002). “Remote electronic control of DNA hybridization through inductive coupling to an attached metal nanocrystal antenna”. Nature, Vol. 415(6868), pp. 152-155.

[9]. Usami M., (2004). “An ultra small RFID chip: µ-chip”. Proceedings of Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 241-244.

[10]. Coil-on-chip RFID tag, Maxell, Fairlawn, NJ, 2010.

[11]. Li Y., Chang C., Lin G. and Lu C., (2013). “Radio Frequency Identification (RFID) Inserted Fixed Prosthesis and its Applications in Clinical Dentistry”. International Journal of Automation and Smart Technology, Vol. 3.

[12]. Brandl M. et al., (2009). “A Low-Cost Wireless Sensor System and Its Application in Dental Retainers”. IEEE Sensors Journal, Vol. 9, No. 3.

[13]. Guan S. et al., (2011). “A Wireless Powered Implantable Bio-Sensor Tag System-on-Chip for Continuous Glucose Monitoring”. Proceedings of IEEE – Biomedical Circuits and Systems Conference (BioCAS).

[14]. Liu X., Lee Berger J., Ogirala A. and, Mickle M. H., (2013). “A Touch Probe Method of Operating an Implantable RFID tag for Orthopedic Implant Identification”. IEEE Transactions on Biomedical Circuits and Systems, Vol. 7, No. 3, pp. 236-242.

[15]. Ricciardi L. et al., (2003). “Investigation into the Future of RFID in Biomedical Applications”. Proceedings of SPIE, Bioengineered and Bioinspired Systems, Vol. 5119.

[16]. Sandeep Reddy M. et al., (2008). “Sensor integration in an RFID tag for monitoring biomedical signals”. th Proceedings of 12 IEEE VLSI Design and Test Symposium, Bangalore, India.

[17]. Zhukov I., Mikhaylov D., and Starikovskiy A., (2012). “Nano sensors integrated into dental implants for detection of acute myocardial infarction”. International Journal of Emerging Trends & Technology in Computer Science (IJETTCS), Vol. 1, No. 2.

[18]. Reicher J., Reicher D., and Reicher M., (2007). “Use of Radio Frequency Identification (RFID) Tags in Bedside Monitoring of Endotracheal Tube Position”. Journal of Clinical Monitoring and Computing, Vol. 21, No. 3 , pp. 155-158.

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Research Paper

Trichotomous Visual Analytics [TVA]: Visual StatisticalCumulative Data Analysis via the Tri–Squared Calculator ADigital Instrument Designed to Present theOutcomes of the Tri–Squared Test

James Edward Osler II*

Faculty Member, Department of Curriculum and Instruction, North Carolina Central University (NCCU) School of Education, USA.

Osler, J. E., II. (2016). Trichotomous Visual Analytics [TVA]: Visual Statistical © Cumulative Data Analysis via the Tri–Squared Calculator A Digital Instrument Designed to Present the Outcomes of the Tri–Squared Test. i-manager's Journal on Electronics Engineering, 6(2), 13-21. https://doi.org/10.26634/jele.6.2.3762

Abstract

This paper presents an innovative digital instrument the Tri–Squared Calculator © that uses the novel Trichotomous Visual Analytics [TVA] as a supportive research model for traditional confirmatory trichotomous statistical analyses. This research adds to the publication entitled, “Trichotomous Exploratory Data Analysis [Tri–EDA]: A Post Hoc Visual Statistical Cumulative Data Analysis Instrument Designed to Present the Outcomes of Trichotomous Investigative Models” published in the imanager's Journal on Instrumentation and Control Engineering. This narrative provides an epistemological rational for the use of “Trichotomous Exploratory Data Analysis” and other trichotomous statistical analytical models for the in–depth analysis of the transformative process of qualitative data into quantitative outcomes through the Tri–Squared Test. The Tri–Squared Test was first introduced in the i-manager’s Journal on Mathematics, and further detailed in the Journal on Educational Technology, Journal on School Educational Technology, and in Journal on Educational Psychology. TVA is used in Tri–Exploratory Data Analysis as a series of graphical and visual statistical models that are a part of the Tri–Squared Calculator ©. The Tri–Squared Calculator © digital instrument was created, designed, and developed by the author to quickly calculate and report Tri–Squared Test outcomes. It also allows the researcher to rapidly check the validity and reliability of Tri–Squared Test results. This is a novel approach to advanced statistical Tri–Squared modeling and reporting. It adds a potent new tool to the mixed methods approach of the trichotomous research design (that intrinsically involves the holistic trichotomous combination and comparison of qualitative and quantitative data outcomes).

References

[1]. Green, T. M., Ribarsky, W., and Fisher, B. (2008). “Visual analytics for complex concepts using a human cognition model”. In Visual Analytics Science and Technology, VAST' 08, IEEE Symposium ,pp. 91-98.

[2]. Heuer, R. J., (1999). Psychology of Intelligence Analysis. Washington De: Central Intelligence Agency.

[3]. Osler, J. E., (2012a). “Trichotomy–Squared – A novel mixed methods test and research procedure designed to analyze, transform, and compare qualitative and quantitative data for education scientists who are administrators, practitioners, teachers, and technologists,” i-manager Journal on Mathematics, Vol.1, No. 3, pp. 23–31.

[4]. Osler, J. E., and Waden, C., (2012b). “Using innovative technical solutions as an intervention for at risk students: A meta–cognitive statistical analysis to determine the impact of ninth grade freshman academies, centers, and center models upon minority student retention and achievement ”. i-manager ’s Journal on School Educational Technology, Vol. 7, No. 3, pp. 11–23.

[5]. Osler, J. E. (2013a). “Algorithmic Triangulation Metrics for Innovative Data Transformation: Defining the Application Process of the Tri–Squared Test”. i-manager's Journal on Mathematics, Vol. 2, No. 2, pp. 10–16.

[6]. Osler, J. E. (2013b). “The Triangulation Algorithmic: A Transformative Function for Designing and Deploying Effective Educational Technology Assessment Instruments”. i-manager's Journal of Educational Technology, Vol. 10 , No. 1, pp. 46–54.

[7]. Osler, J. E. (2014a). “Triostatistics: The Application of Innovative In–Depth Advanced Post Hoc Statistical Metrics for the Assessment and Analysis of Statistically Significant Tri–Squared Test Outcomes”. Kentucky Journal of Excellence in College Teaching and Learning, Vol. 12, No. 3, pp. 27–39.

[8]. Osler, J. E., (2014b). “Introducing TRINOVA: “Trichotomous Nomographical Variance” A Post Hoc Advanced Statistical Test of Between and Within Group Variances of Trichotomous Categorical and Outcome Variables of a Significant Tri–Squared Test”. i-manager's Journal on Mathematics, Vol. 3, No. 4, pp. 1–14.

[9]. Osler, J. E., (2015). “Trichotomous Exploratory Data Analysis [Tri–EDA]: A Post Hoc Visual Statistical Cumulative Data Analysis Instrument Designed to Present the Outcomes of Trichotomous Investigative Models”. i-manager's Journal on Instrumentation and Control Engineering, Vol. 3, No. 3, pp. 11–20.

[10]. Pike, W., May, R., Baddeley, B., Riensche, R., Bruce, J., and Younkin, K. (2007). “Scalable visual reasoning: supporting collaboration through distributed analysis”. In Collaborative Technologies and Systems, CTS. International Symposium on, pp. 24-32 .

[11]. Rosenberg, M., (1968). The Logic of Survey Analysis. New York: Basic Books.

[12]. Vygotsky, L. S., (1980). Mind in Society: The Development of Higher Psychological Processes. Harvard University Press.

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Research Paper

Voltage Mode Second Order Notch/All - PassFilter Realization Using OTRA

Rashika Anurag* , Neeta Pandey, Rohan Chandra*, Rajeshwari Pandey****

* Associate Professor, Department of Electronics and Communication Engineering, JSS Academy of Technical Education, NOIDA, India.

_** Associate Professor, Department of Electronics and Communication Engineering, Delhi Technological University, Delhi, India.

Anurag, R., Pandey, N.,Chandra, R., and Pandey, R. (2016). Voltage Mode Second Order Notch/All - Pass Filter Realization Using OTRA. i-manager's Journal on Electronics Engineering, 6(2), 22-28. https://doi.org/10.26634/jele.6.2.3763

Abstract

This paper presents a Second Order Notch/All pass filter based on Operational Transresistance Amplifier (OTRA). It uses two OTRA's and five resistances. To add electronic tunability, the filter uses a capacitor array that can be controlled by switches. The switches are also used to provide inverting and non inverting Notch/All pass as response. This adds flexibility in phase response of all pass filter. The notch/all pass configuration is a modified extension of the Delyiannis-Friend circuit. Through the addition of a second active block which basically acts as a summer for the input voltage and the output of the first OTRA block. The functionality of the proposed filters is verified through SPICE simulations using CMOS based implementation of OTRA. The power supply for the implementation is 1.5V and is based on 0.5 submicron technology.

References

[1]. Cakir, C., Cam, U., and Cicekoglu, O., (2005). “Novel all pass filter configuration employing single OTRA”. IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.52, No. 3, pp. 122-125.

[2]. Cam, U., Kacar, F., Cicekoglu, O., Kuntman, H., and Kuntman, A. (2003). “Novel Grounded Parallel Immittance Simulator Topologies Employing Single OTRA”. AEU - International Journal of Electronics and Communications, Vol. 57, No. 4, pp. 287-290.

[3]. Chang, C., Ko, Y., Guo, Z., Hou, C., and Horng, J. (2015). “Generation of Voltage-Mode OTRA-R/MOS-C LP, BP, HP, and BR Biquad Filter”. Wisconsin: IMCAS'11. pp. 28- 34.

[4]. Chen, J., Tsao, H., and Liu, S., (2001). “Voltage-mode MOSFET-C filters using operational transresistance amplifiers (OTRAs) with reduced parasitic capacitance effect”. IEEE Proceedings - Circuits, Devices And Systems, Vol. 148, No. 5, pp. 242.

[5]. Chen, J., Tsao, H., Liu, S., and Chiu, W., (1995). “Parasitic-capacitance-insensitive current-mode filters using operational transresistance amplifiers”. IEEE Proceedings - Circuits, Devices And Systems, Vol. 142, No. 3, 186.

[6]. Chien, H., (2014). “New Realizations of Single OTRABased Sinusoidal Oscillators”. Active And Passive Electronic Components, 2014, pp. 1-12.

[7]. Gokcen, A., and Cam, U., (2009). “MOS-C single amplifier biquads using the operational transresistance amplifier”. AEU - International Journal of Electronics and Communications, Vol. 63, No. 8, pp. 660-664.

[8]. Gokcen, A., Kilinc, S., and Cam, U., (2011). “Fully Integrated Universal Biquads Using Operational Transresistance Amplifiers With MOS-C Realization”. Turkish Journal Of Electrical Engineering And Computer Sciences, Vol. 19, No. 3, pp. 363-372.

[9]. Kilinc, S., and Cam, U., (2005). “Cascadable allpass and notch filters employing single operational transresistance amplifier ”. Computers & Electrical Engineering, Vol. 31, No. 6, pp. 391- 401.

[10]. Kilinc, S., Keskin, A., and Cam, U. (2007). “Cascadable Voltage-Mode Multifunction Biquad Employing Single OTRA”. Frequenz, Vol. 61, pp. 3-4.

[11]. Lo, Y., Chien, H., and Chiu, H. (2009). “Current-input OTRA Schmitt trigger with dual hysteresis modes”. Int. J. Circ. Theor. Appl., Vol. 38(7), pp. 739-746.

[12]. Mostafa, H., and Soliman, A., (2006). “A Modified CMOS Realization of the Operational Transresistance Amplifier (OTRA)”. Frequenz, Vol. 60, pp. 3-4.

[13]. Pandey, R., Pandey, N., Paul, S., Singh, A., Sriram, B., and Trivedi, K. (2012). “Voltage Mode OTRA MOS-C Single Input Multi Output Biquadratic Universal Filter”. AEEE, Vol. 10, No. 5.

[14]. Pandey, R., Pandey, N., Sriram, B., and Paul, S. (2012). “Single OTRA Based Analog Multiplier and Its Applications”. ISRN Electronics, 2012, pp. 1-7.

[15]. Salama, K., and Soliman, A. (1999). “CMOS operational transresistance amplifier for analog signal processing”. Microelectronics Journal, Vol. 30, No. 3, pp. 235-245.

[16]. Salama, K., and Soliman, A. (2000). “Novel oscillators using the operational transresistance amplifier”. Microelectronics Journal, Vol. 31, No. 1, pp. 39-47.

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Research Paper

Comparative Analysis and FPGA Implementationof Vedic and Booth Multiplier

Parul Agrawal* , Rahul Sinha**

* PG Scholar, Department of Electronics and Telecommunication, C.S.I.T, Durg, India.

** Assistant Professor, Department of Electronics and Telecommunication, C.S.I.T, Durg, India.

Agrawal, P., and Sinha, R. (2016). Comparative Analysis and FPGA Implementation of Vedic and Booth Multiplier. i-manager's Journal on Electronics Engineering, 6(2), 29-35. https://doi.org/10.26634/jele.6.2.3764

Abstract

The digital computing systems like mathematical co-processors, micro-processors, digital filters must be highly efficient in terms of computational time. The most fundamental operation in any computing systems is multiplication. The multiplier should therefore employ minimum processing time by the use of high speed adders. This paper describes the design of Vedic Multiplier using Kogge Stone Adder (the fastest Parallel Prefix Adder) and Booth Multiplier (based on two's complement notation). The two designs have been compared based on delay, levels of logic, number of slices, and memory usage. Based on the synthesis report obtained, the delay in Booth Multiplier has been found to be very less compared to Vedic Multiplier however, during simulation in Booth Multiplier the response to the inputs is not instantaneous, but there is a large amount of wait period in getting the output as the count signal increments in the sequential circuit which is not the case with Vedic Multiplier (Combinational Circuit). This showed that the Booth Multiplier is slower compared to Vedic Multiplier. The two designs have been implemented in Xilinx ISE 14.4 for the family of devices Spartan 6 with the device name Xc6slx45, package csg324,and speed grade of -3.

References

[1]. Booth A.D. (1951). “A signed binary multiplication technique”. Quarterly Journal of Mechanics and Applied Mathematics, Vol. 4, No. 2, pp. 236– 240.

[2]. Goyal Neha, Gupta Khushboo and Singla Renu, (2014). “Study of Combinational and Booth Multiplier”. International Journal of Scientific and Research Publications, Vol. 4, No. 5, pp. 1-4.

[3]. Harris D., (2003). “A Taxonomy of Parallel Prefix th Networks”. in Proc. 37 Asilomar Conf. Signals Systems and Computers, pp. 2213–7.

[4]. Hoe David, Martinez Chris and Vundavalli Jyothsna Sri. (2011). “Design and Characterization of Parallel Prefix rd Adders using FPGAs”, IEEE 43 South Eastern Symposium Auburn, AL. pp. 168-172.

[5]. Kumar G., (2012). “Design of High Speed VM using Vedic Mathematics Techniques”. International Journal of Scientific and Research Publications, Vol. 2, No. 3, pp. 1- 5.

[6]. Kumar Sudheer, and Naik Rajendra, (2014). “Design and Estimation of delay, power, area for Parallel Prefix Adders”. RAECS, Chandigarh .

[7]. Mano Morris M., (1979). Digital Logic and Computer Design. Pearson Education.

[8]. M. Poornima, Patil Shivaraj, Shivukumar, K.P Shridhar, H. Sanjay, (2013). “Implementation of Multiplier using Vedic Algorithm”. IJITEE , Vol. 2, No. 6, pp. 219-223.

[9]. Palnitkar Samir., (1996). Verilog HDL: A Guide to Digital Design and Synthesis. SunSoftPress.

[10]. Pohokar S.P, Sisal R.S., Gaikwad K.M., Patil M.M., and Borse Rushikesh, (2015). “Design & Implementation of 16x16 multiplier using Vedic Mathematics”. IEEE Conference ICIC, Pune.

[11]. R. Anjana, B. Abishna, M.S. Harshitha, E. Abhishek, V. Ravichandra, and M.S. Suma, (2014). “Implementation of VM using Kogge Stone Adder”. IEEE Conference ICES, Coimbatore.

[12]. Tirthaji Bharti Krishna, (1965). “Vedic Mathematics or Sixteen Simple Mathematical Formulae from the Veda”. Motilal Banarsidas Varanasi, India.

[13]. Wakerly John F., (1999). ‘Digital Design Principles and Practices. Prentice Hall.

[14]. Parul Agrawal and Rahul Sinha, (2015). “Comparative Analysis and FPGA Implementation of Vedic Multiplier for various Bit Lengths using Different Adders”. International Journal of Innovative Research in Computer and Communication Engineering, Vol. 3, No. 10.

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Research Paper

A Novel Multilevel Inverter with Minimum Switches

Manjunatha B.M.* , Ashok Kumar D.V., Vijay Kumar M.*

* Assistant Professor, Department of Electrical and Electronics Engineering, Rajeev Gandhi Memorial College of Engineering and Technology, Nandyal, Andhra Pradesh, India.

Dean and Professor, Department of Electrical and Electronics Engineering, Rajeev Gandhi Memorial College of Engineering and Technology, Nandyal, Andhra Pradesh, India.

* Professor, Department of Electrical and Electronics Engineering, Jawaharlal Nehru Technological University, Anantapur, Andhra Pradesh, India.

Manjunatha, B.M., Kumar, D.V.A., and Kumar, M.V. (2016). A Novel Multilevel Inverter with Minimum Switches. i-manager's Journal on Electronics Engineering, 6(2), 36-41. https://doi.org/10.26634/jele.6.2.3766

Abstract

This paper presents an unique three phase seven level inverter with reduced number of switches. Multilevel Inverters (MLI) are used in high power and high voltage applications as they are capable of producing multiple levels in output voltage with reduced THD. To reduce THD further, the number of levels in the output voltage has to be increased, which is directly associated with the number of switches required. To accomplish this, the conventional MLI experiences complexity in control, number of required DC sources, size, switching losses and cost of overall system increases. The proposed topology overcomes the aforesaid limitations and compared with the conventional MLI in terms of the number of switches, DC sources, capacitors, fundamental voltage, and THD. The performance is analyzed by using a simulation tool.

References

[1]. Marchesoni. M, (2002). “Diode-clamped multilevel converters: a practicable way to balance DC-link voltages”. Industrial Electronics, IEEE Transactions, Vol. 49, No. 4, pp. 752-765.

[2]. Escalante, Miguel F. Jean-Claude Vannier, and Amir Arzande, (2002). "Flying capacitor multilevel inverters and DTC motor drive applications." Industrial Electronics, IEEE Transactions on , Vol. 49, No. 4 , pp. 809-815.

[3]. Mariusz Malinowski, K. Gopakumar, Jose Rodriguez and Marcelo A. Perez, (2010). “A Survey on Cascade Multilevel inverters”. IEEE Trans. Ind. Electron, Vol. 57, No. 7.

[4]. Franquelo. L. G., Rodriguez. J., Leon. S., Kouro. J. I., Portillo. R , and Prats. M. A., (2008). “The age of multilevel converters arrives”. IEEE Ind. Electron. Mag, Vol. 2, No. 2, pp. 28–39.

[5]. Nimitha, M. and Ramani T., (2014).“Simulation & analysis of multilevel inverter with reduced number of switches”. IJEET, Vol. 5, No .12.

[6]. Gnana Prakash M., Balamurugan M., and Umashankar S., (2014). “A New Multilevel Inverter with reduced number of switches”. IJPEDS, Vol. 5, No. 1.

[7]. S. Nagaraja Rao, D.V. Ashok Kumar. and Ch. Sai Babu, (2013).“New Multilevel Inverter Topology with reduced number of switches using advanced Modulation Strategy ”.In: Proceedings of the International Conference on Power, Energy and Control (ICPEC).

[8]. Manjunatha B. M, Ashok Kumar D. V. and Vijay Kumar, M. (2015). “Advanced Pulse Width Modulation Techniques for Z Source Multi Level Inverter”. World Academy of Science, Engineering and Technology, International Science Index 99, International Journal of Electrical, Computer, Energetic, Electronic and Communication Engineering, Vol. 9, No. 3, pp. 337 - 342.

[9]. Brendan Pete McGrath and Donald Grahame Holmes, (2002). “Multicarrier PWM Strategies for Multilevel Inverters”. IEEE Trans.Ind. Electronics, Vol. 49, No. 4.

i-manager's Journal on Electronics Engineering (JELE)

Current Issue Vol. 15 Issue 1

Most Read

Most Cited

Volume 6 Issue 2 December - February 2016 [Open Access]

RFID Technology for Biomedical Applications: State of Art and Future Developments

Roberto Marani* , 0**

* Researcher, Consiglio Nazionale Delle Ricerche, Istituto di Studi sui Sistemi Intelligenti per l'Automazione (ISSIA), Bari, Italy. ** Full Professor, Electronics and Head of Electronic Devices Laboratory, Department of Electrical and Information Engineering, Polytechnic University of Bari, Italy.

Marani, R., and Perri, A.G. (2016). RFID Technology for Biomedical Applications: State of Art and Future Developments. i-manager's Journal on Electronics Engineering, 6(2), 1-12. https://doi.org/10.26634/jele.6.2.3761

Abstract

References

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Trichotomous Visual Analytics [TVA]: Visual StatisticalCumulative Data Analysis via the Tri–Squared Calculator ADigital Instrument Designed to Present theOutcomes of the Tri–Squared Test

James Edward Osler II*

Faculty Member, Department of Curriculum and Instruction, North Carolina Central University (NCCU) School of Education, USA.

Abstract

References

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Voltage Mode Second Order Notch/All - PassFilter Realization Using OTRA

Rashika Anurag* , Neeta Pandey**, Rohan Chandra***, Rajeshwari Pandey****

* Associate Professor, Department of Electronics and Communication Engineering, JSS Academy of Technical Education, NOIDA, India. **_**** Associate Professor, Department of Electronics and Communication Engineering, Delhi Technological University, Delhi, India.

Anurag, R., Pandey, N.,Chandra, R., and Pandey, R. (2016). Voltage Mode Second Order Notch/All - Pass Filter Realization Using OTRA. i-manager's Journal on Electronics Engineering, 6(2), 22-28. https://doi.org/10.26634/jele.6.2.3763

Abstract

References

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Comparative Analysis and FPGA Implementationof Vedic and Booth Multiplier

Parul Agrawal* , Rahul Sinha**

* PG Scholar, Department of Electronics and Telecommunication, C.S.I.T, Durg, India. ** Assistant Professor, Department of Electronics and Telecommunication, C.S.I.T, Durg, India.

Agrawal, P., and Sinha, R. (2016). Comparative Analysis and FPGA Implementation of Vedic and Booth Multiplier. i-manager's Journal on Electronics Engineering, 6(2), 29-35. https://doi.org/10.26634/jele.6.2.3764

Abstract

References

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A Novel Multilevel Inverter with Minimum Switches

Manjunatha B.M.* , Ashok Kumar D.V.**, Vijay Kumar M.***

Manjunatha, B.M., Kumar, D.V.A., and Kumar, M.V. (2016). A Novel Multilevel Inverter with Minimum Switches. i-manager's Journal on Electronics Engineering, 6(2), 36-41. https://doi.org/10.26634/jele.6.2.3766

Abstract

References

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Rashika Anurag* , Neeta Pandey, Rohan Chandra*, Rajeshwari Pandey****

* Associate Professor, Department of Electronics and Communication Engineering, JSS Academy of Technical Education, NOIDA, India.

_** Associate Professor, Department of Electronics and Communication Engineering, Delhi Technological University, Delhi, India.

* PG Scholar, Department of Electronics and Telecommunication, C.S.I.T, Durg, India.

** Assistant Professor, Department of Electronics and Telecommunication, C.S.I.T, Durg, India.

Manjunatha B.M.* , Ashok Kumar D.V., Vijay Kumar M.*