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i-manager's Journal on Electronics Engineering (JELE)

Current Issue Vol. 15 Issue 1

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Volume 4 Issue 1 September - November 2013

Article

Performance Comparison of Carbon Nanotube, Graphene Nano Ribon and Silicon Nanowire Transistors

S. B. Siddique* , T. M. Faruqi, B.C. Sarkar*, Mahmudul Hasan****

, , Electronics and Electrical Engineering.

****Assistant Professor, Electronics and Communication Engineering, University of Information Technology and Sciences, Dhaka 1212, Bangladesh.

Siddique, S.B., Faruqi, T. M., Sarkar, B.C., and Hasan, M. (2013). Performance Comparison Of Carbon Nanotube, Graphene Nano Ribon And Silicon Nanowire Transistors. i-manager’s Journal on Electronics Engineering, 4(1), 1-10. https://doi.org/10.26634/jele.4.1.2508

Abstract

Graphene Nanoribbons(GNR) and Carbon Nanotubes(CNT) represent a novel class of low-dimensional materials. These Graphene based nanostructures are used in wide range of nanoscience and nanotechnology applications. In this article, the performance potential of ballistic Graphene and Silicon Nanowire(SiNW) field effect transistors are examined for future high-performance applications. A thorough investigation has been made to realize the performance of these three types of transistors in terms of drain current, transconductance, number of mobile charge, quantum capacitance, gate capacitance, gate delay and cut off frequency using ballistic top of the barrier model. On-current, transconductance and gate capacitance control the switching speed of a transistor. It is shown that, the on-current in carbon based channel is higher as well as ION/IOFF is higher than SiNW channel due to lower effective mass. Higher on-current indicates sharper slope in current curve which ensures higher transconductance. It is also shown that the density of states(DOS) of CNT and GNR transistors are lower than the SiNW transistor. Through extensive computer simulation it is shown that the Graphene transistors can be the candidates for future digital switches. It is also important that SiNW transistors in are potentially attractive, given the central role of silicon in the semiconductor industry and the existing set of known fabrication technologies.

References

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[3]. Moore, G.(1975). Progress in Digital Integrated Electronics.IEEE Tech., Digest, pp.11-13

[4]. Jeroen, W. G.,et al.(1998), Electronic structure of atomically resolved carbon nanotubes. Nature, Vol. 391, pp. 59

[5]. Curutchet A., (2008). et al.Nonlinear Characterization and Modeling of Carbon Nanotube Field-Effect Transistors. Microwave Theory and Techniques. IEEE Transactions on, Vol. 56(7), pp. 1505-1510,

[6]. Ngo, Q.,Petranovic,D.,Krishnan, S.,Cassell, A. M.,Ye, Q., Li,J., Meyyappan, M.,&Yang, C. Y. (2004). Electron Transpor tin Multi wall Carbon Nano tubes . Nanotechnology, IEEE Transactions on., Vol. 3(2), pp. 311- 317

[7]. Wagner, R. S. & Ellis,W.C. (1964). Vapor Liquid Solid Mechanism of Single Crystal Groth, Appl. Phys. Lett.,Vol. 4,pp.89-90

[8]. Sorokin,P. B., et al. (2010). Metallic beta-phase silicon nanowires: Structure and electronic properties, JETP Letters, Vol.92 (5). pp. 352-355

[9]. Schmidt,V., Wittemann,J. V., Gösele,U. (2010). Growth,Thermodynamics, and Electrical Properties of Silicon Nanowires, American Chemical Society, Vol. 110 (1), pp. 361-388.

[10] . A r a d i , B . , R a m o s , L . E . , D e á k , P. , K ö h l e r, Th.,Bechstedt,F.,Zhang, R. Q., & Frauenheim,Th. (2007). Theoretical study of the chemical gap tuning in silicon nanowires, Vol. 76 (3).

[11]. Lemme, M. C. (2010). Current Status of Graphene Transistors. Solid State Phenomena, Vol. 156-158,pp. 499- 509.

[12]. Sako, R., Tsuchiya, H.,&Ogawa, M. (2011). Influence of Band-Gap Opening on Ballistic Electron Transport in Bilayer Graphene and Graphene Nanoribbon FETs.Electron Devices, IEEE Transactions on, Vol. 58 (10),pp. 3300-3306.

[13]. Ouyang, Y., Yoon, Y.,&Jing,G. (2007). Scaling Behaviors of Graphene Nanoribbon FETs: A Three Dimensional Quantum Simulation Study, IEEE Transactions on Electron Devices, Vol. 54, pp. 2223-2231

[14]. Javey, A.,Guo, J.,Wang,Q., Lundstrom, M.,& Dai,H. J. (2003). Ballistic carbon nanotube field-effect transistors. Nature, vol. 424, pp. 654-657.

[15]. Guo, J.&Lundstrom,M. S. (2002). A computational study of thin body, double-gate, Schottky barrier MOSFETs. IEEE Trans. on Electron Dev., Vol. 49, pp. 1897-1902.

[16]. Rahman,A., Guo,J., Datta, S.& Lundstrom, M. (2003). Theory of ballistic nanotransistors. IEEE Trans. Electron Dev., Vol. 50 (9), pp. 1853-1864.

[17]. Ouyang, Y.,Yoon, Y.,Fodor, J. K.,& Guo,J. (2006). Comparison of performancelimitsfor carbon nanoribbon and carbon nanotube transistors. Applied Physics Letters, Vol. 89, pp. 203107.1-203107.3.

[18]. Lundstrom, M. & Guo,J. (2006). Nanoscale transistors: device physics, modeling and simulation, New York: Springer, Vol. 8,pp. 224.

[19]. Khan, A.,Ashraf, M.Haque, A. (2009). Wave function penetration effects in double gate metal-oxidesemiconductor field-effect-transistors: impact on ballistic drain current with device scaling. Journal of Applied Physics, Vol.105(6),pp. 064505 - 064505-5

[20]. Gildenblat, G., Li, X., Wu, W., Wang, H., Jha, A., Langevelde, R. V., et al. (2006). PSP: anadvanced surface-potential-based MOSFET model for circuit simulation, IEEE Trans. Electron. Dev., 53(9), pp. 1979-93

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Research Paper

Binary Morphology With Image Compression And Cryptography

Ponshankar B* , Swaranambigai R.**

* ME (Applied Electronics), Jay shriram group of institutions, Anna University, Coimbatore

** Assistant Professor (ECE), Jay shriram group of institutions, Anna University, Coimbatore

Ponshankar, B., and Swaranambigai, R. (2013). Binary Morphology with Image Compression and Cryptography. i-manager’s Journal on Electronics Engineering, 4(1), 11-17. https://doi.org/10.26634/jele.4.1.2509

Abstract

Binary Image processing is extremely useful in various areas, such as object recognition, tracking, motion detection, machine intelligence, image analysis, understanding video processing, computer vision, and identification and authentication systems. Binary image processing (BIP) has been commonly implemented using processors such as CPU or DSP. However, it is inefficient and difficult to use such processors for binary image processing. High-speed implementation of binary image processing operations can be efficiently realized by using chips specialized for binary image processing. Mathematical morphology(MM) is a nonlinear image processing framework used to manipulate or analyze the shape of functions or objects. Mathematical morphology(MM) is set theory-based methods of image analysis and plays an important role in many digital image processing algorithms and applications, e.g., noise filtering, object extraction, analysis or pattern recognition. The methods, originally developed for binary images, were soon extended and now apply to many different image representations. Real-time image processing systems have constraints on speed or hardware resources. In addition, in embedded or mobile applications, this system consumes low power and low memory. The cryptography involves efficient algorithms related to encryption and decryption.

References

[1]. Bin Zhang, Kuizhi Mei and Nanning Zheng, (2013). “Reconfigurable Processor for Binary Image Processing”, in IEEE transactions on circuits and systems for video technology, Vol. 23, No. 5,

[2]. P. Dokladal, H. Hedberg, and V. Owall, (2009). “Binary morphology with spatially variant structuring elements algorithm and architecture,” IEEE Trans. Image Process., Vol. 18, No. 3, pp. 562–572, Mar.

[3]. Hugo Hedberg, Fredrik Kristensen, Viktor Öwall, (2008). “Low-Complexity Binary Morphology Architectures With Flat Rectangular Structuring Elements,” in IEEE transactions on circuits and systems—i: regular papers, Vol. 55, No. 8, september.

[4]. Huijuan Yang and Alex C. Kot, (2006). “Image authentication with tampering localization by embedding cr yptographic signature and block identifier,” in IEEE signal processing letters, Vol. 13, No. 12, december.

[5]. Min Wu, and Bede Liu, (2004). “Data Hiding in Binary Image for Authentication and Annotation”, in IEEE Transactions On Multimedia, Vol. 6, No. 4, August.

[6]. E. C. Pedrino, O. Morandin, Jr., and V. O. Roda, (2011). “Intelligent FPGA based system for shape recognition,” in Proc. 7th Southern Conf. Programmable Logic, pp. 197–202.

[7]. E. C. Pedrino, J. H. Saito, and V. O. Roda, (2010). “Architecture for binary mathematical morphology reconfigurable by genetic programming,” in Proc. 6th Southern Programmable Logic Conf., pp. 93–98.

[8]. E. N. Malamas, A. G. Malamos, and T. A. Varvarigou, (2000). “Fast implementation of binary morphological operations on hardware-efficient systolic architectures,” J. VLSI Signal Process., Vol. 25, No. 1, pp. 79–93.

[9]. S. Chien and L. Chen, (2011). “Reconfigurable morphological image processing accelerator for video object segmentation,” J. Signal Process. Syst., vol. 62, no. 1, pp. 77–96,

[10]. N. Bouaynaya, M. Charif-Chefchaouni, and D. Schonfeld, (2006). “Spatiallyvariant morphological restoration and skeleton representation,” IEEE Trans. Image Process., Vol. 15, pp. 3579–3591,

[11]. Ganesh Chandra, D.L. Gupta, Dr. A.K. Malviya, Satyendra Singh, Vinod Kumar Yadav, (2012). “Public Key Cryptosystem Technique Elliptic Curve Cryptography with Generator g for Image Encryption”, Int. J. Computer Technology & Applications, Vol 3 (1), 298-302.

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Research Paper

Performance Analysis of Low-Density Parity-Check Codes for M-QAM Systems

Hirald Dwaraka Praveena* , 0, N. Padmaja*

* Asst. Professor, Dept of ECE, Sree Vidyanikethan Engineering College, Tirupati.

** Professor, Dept of ECE, Sree Vidyanikethan Engineering College, Tirupati.

Praveena, K.D., Subhas, C., and Padmaja, N. (2013). Performance Analysis of Low-Density Parity-Check Codes for M-Qam Systems. i-manager’s Journal on Electronics Engineering, 4(1), 18-23. https://doi.org/10.26634/jele.4.1.2511

Abstract

Low-Density Parity-Check codes are state-of-art error detecting and correcting codes, include several standards of broadcast transmissions. Iterative message passing decoding algorithms for LDPC codes have excellent error correction capability. Low computational complexity combined with parallelism and good error correcting performance are the reasons of choosing LDPC codes. The reliability of received data depends on the channel and external noise that could interfere with the signal. Error correcting codes (ECCs) are used to detect and correct errors thereby increasing the system throughput, speed and reducing power consumption. Error detection and correction is achieved by adding redundant symbols to the original data. Modern telecommunication standards adopt higher order modulation schemes, such as M-QAM to achieve large spectral efficiency. In this paper it is shown that the LDPC codes are the best choice in complex environment compared to turbo codes.

References

[1]. Berrou,C, Glavieux, A. & Thitimajshima, P. (1993). “Near shannon limit error-correcting coding and decoding: Turbo-codes,” Proceedings ICC (Geneva), IEEE, pp. 1064–1070.

[2]. Marco Baldi, Franco Chiaraluce, (2009). Member, IEEE, and Giovanni Cancellieri “Finite- Precision Analysis of De-mappers and Decoders for LDPC-Coded M-QAM Systems,” IEEE Transactions on broadcasting, Vol. 55, No. 2.

[3]. Gallager, R. G. (1963). “Low-Density Parity-Check Codes,” Cambridge, MA: MIT Press,

[4]. MacKay, D.& Neal, R. “Near Shannon limit performance of low density parity check Code,” Electronics Letters, Vol. 33, No 6, pp. 457–458.

[5]. DVB-RCS (2000). ETSI EN 301 790, V1.2.2

[6]. Hu, X.Y, Eleftheriou, E. Arnold, D. M. & Dholakia, A. (2001). “Efficient implementations of the sum-product algorithm for decoding LDPC codes,” in Proc. IEEE Global Telecomm. Conference, San Antonio, Vol. 2, pp. 1036E–1036E.

[7]. Richardson, T. & Urbanke, R. (2001). “The capacity of low-density parity- check codes under message-passing decoding,” IEEE Trans. Inform. Theory, Vol. 47, No. 2, pp. 599–618.

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Research Paper

A Survey Of New Reconfigurable Architectures For Implementing FIR Filters With Low Complexity

V. Sandhiya* , S. Karthick, M. Valarmathy*

* Second year PG scholar, Department of Electronics and Communication Engineering, Bannari Amman Institute of Technology, Sathyamangalam, Erode-638401,Tamilnadu, INDIA.

Assistant professor, Department of Electronics and Communication Engineering, Bannari Amman Institute of Technology, Sathyamangalam, Erode-638401,Tamilnadu, INDIA

* Professor and Head, Department of Electronics and Communication Engineering, Bannari Amman Institute of Technology, Sathyamangalam, Erode-638401,Tamilnadu, INDIA

Sandhiya, V., Karthick, S., and Valarmathy, M. (2013). A Survey Of New Reconfigurable Architectures For Implementing FIR Filters With Low Complexity. i-manager’s Journal on Electronics Engineering, 4(1), 29-39. https://doi.org/10.26634/jele.4.1.2513

Abstract

Finite Impulse Response (FIR) filters are widely used in multistandard wireless communications. The two key requirements of FIR filters are reconfigurabilty and low complexity. The researches have been introduced many architectures for above key metrics. For reconfigurable FIR filter, two architectures was implemented, namely Constant Shift Method [CSM] and Programmable Shift Method [PSM]. The complexity of linear phase FIR filters is dominated by the number of adders (subtractors) in the coefficient multiplier. The Common Subexpression Elimination (CSE) algorithm was introduced for reducing the number of adders in the multipliers and also dynamically reconfigurable filters can be efficiently implemented based on Canonic Signed Digit (CSD) representation of coefficients. It is well known that the two classes of Common Subexpression Elimination techniques(vertical and horizontal) minimize the two main cost metrics namely logic operators and logic in realizing finite impulse response (FIR) filters. A new CSE algorithm using binary representation of coefficients was introduced for the implementation of higher order FIR filters with a fewer number of adders than CSD-based CSE methods. A new greedy CSE algorithm based on CSD representation of coefficients multipliers was introduced for implementing low complexity higher order filters. Design examples shows that the filter architectures offer power reduction and good area and speed improvement over the existing FIR implementation.

References

[1]. Hentschel and G. Fettweis, (1999). “Software radio receivers,” in CDMA Techniques for Third Generation Mobile Systems. Dordrecht, The Netherlands: Kluwer Academic,pp.257-283.

[2]. J. Mitola, (2000). “Object-oriented approaches to wireless systems engineering,”in Software Radio Architecture. New York: Wiley,

[3]. A. P. Vinod and E. Lai, (2006). “Low power and high speed implementation of FIR filters for software defined radio receivers,” IEEE Trans. Wireless Commun., Vol. 5, No. 7, pp. 1669–1675, Jul.

[4]. R. I. Hartley, (1996). “Subexpression sharing in filters using canonic signed digit multipliers,” IEEE Trans. Circuits Syst. II, Vol. 43, No. 10, pp. 677–688, Oct.

[5]. R. Pasko, P. Schaumont, V. Derudder, S. Vernalde, and D. Durackova, (1999). “A new algorithm for elimination of common subexpressions,” IEEE Trans. Comput.-Aided Design Integr. circuits Syst., vol. 18, no. 1, pp. 58–68, Jan.

[6]. M. M. Peiro, E. I. Boemo, and L. Wanhammar, (2002). “Design of high-speed multipliersless filters using a nonrecursive signed common subexpression algorithm,” IEEE Trans. Circuits Syst. II, Vol. 49, No. 3, pp. 196–203,

[7]. A. P. Vinod and E. M.-K.Lai, (2005). “On the implementation of efficient channel filters for wideband receivers by optimizing common subexpression elimination methods,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., Vol. 24, No. 2, pp. 295–304,

[8]. R. Mahesh and A. P. Vinod, (2008). “A new common subexpression elimination algorithm for realizing low complexity higher order digital filters,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., Vol. 27, No. 2, pp. 217–219,

[9]. A. P. Vinod and E. Lai, (2006). “Low power and highspeed implementation of FIR filters for software defined radio receivers,” IEEE Trans. Wireless Commun., Vol. 5, No. 7, pp. 1669–1675, Jul.

[10]. K. Muhammad and K. Roy, (2002). “Reduced computational redundancy implementation of DSP algorithms using computation sharing vector scaling,” IEEE Trans. Very Large Scale Integr. Syst., Vol. 10, No. 3, pp. 292–300,

[11]. K. H. Chen and T. D. Chiueh, (2006). “A low-power digit-based reconfigurable FIR filter,” IEEE Trans. Circuits Syst. II, Vol. 53, No. 8, pp. 617–621,

[12]. T. Zhangwen, J. Zhang, and H. Min, (2002). “A highspeed, programmable, CSD coefficient FIR filter,” IEEE Trans. Consumer Electron., Vol. 48, No. 4, pp. 834–837,

[13]. X. Chenghuan, C. He, Z. Shunan, and W. Hua, (2003). “Design and implementation of a high speed programmable polyphase FIR filter,” in Proc. 5th Int. Conf. Applicat.-Specific Integr. Circuit, Vol. 2., pp. 783–787.

[14]. S. S. Demirsoy, I. Kale, and A. G. Dempster, (2004). “Efficient implementation of digital filters using novel reconfigurable multiplier blocks,” in Proc. 38th Asilomar Conf. Signals Syst. Comput., Vol. 1. pp. 461– 464.

[15]. P. Tummeltshammer, J. C. Hoe, and M. Puschel, (2007). “Multiplexed multiple constant multiplication,” IEEE Trans. Comput.-Aided Design Integr. Circuits, Vol. 26, No. 9, pp. 1551–1563,

[16]. J. Park, W. Jeong, H. Mahmoodi-Meimand, Y. Wang, H. Choo, and K.Roy, (2004). “Computation sharing programmable FIR filter low-power and highperformance applications,” IEEE J. Solid State Circuits, Vol. 39, No. 2, pp. 348–357,

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i-manager's Journal on Electronics Engineering (JELE)

Current Issue Vol. 15 Issue 1

Most Read

Most Cited

Volume 4 Issue 1 September - November 2013

Performance Comparison of Carbon Nanotube, Graphene Nano Ribon and Silicon Nanowire Transistors

S. B. Siddique* , T. M. Faruqi**, B.C. Sarkar***, Mahmudul Hasan****

*, **, *** Electronics and Electrical Engineering. ****Assistant Professor, Electronics and Communication Engineering, University of Information Technology and Sciences, Dhaka 1212, Bangladesh.

Siddique, S.B., Faruqi, T. M., Sarkar, B.C., and Hasan, M. (2013). Performance Comparison Of Carbon Nanotube, Graphene Nano Ribon And Silicon Nanowire Transistors. i-manager’s Journal on Electronics Engineering, 4(1), 1-10. https://doi.org/10.26634/jele.4.1.2508

Abstract

References

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Binary Morphology With Image Compression And Cryptography

Ponshankar B* , Swaranambigai R.**

* ME (Applied Electronics), Jay shriram group of institutions, Anna University, Coimbatore ** Assistant Professor (ECE), Jay shriram group of institutions, Anna University, Coimbatore

Ponshankar, B., and Swaranambigai, R. (2013). Binary Morphology with Image Compression and Cryptography. i-manager’s Journal on Electronics Engineering, 4(1), 11-17. https://doi.org/10.26634/jele.4.1.2509

Abstract

References

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Performance Analysis of Low-Density Parity-Check Codes for M-QAM Systems

Hirald Dwaraka Praveena* , 0**, N. Padmaja***

* Asst. Professor, Dept of ECE, Sree Vidyanikethan Engineering College, Tirupati. ** Professor, Dept of ECE, Sree Vidyanikethan Engineering College, Tirupati.

Praveena, K.D., Subhas, C., and Padmaja, N. (2013). Performance Analysis of Low-Density Parity-Check Codes for M-Qam Systems. i-manager’s Journal on Electronics Engineering, 4(1), 18-23. https://doi.org/10.26634/jele.4.1.2511

Abstract

References

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A Survey Of New Reconfigurable Architectures For Implementing FIR Filters With Low Complexity

V. Sandhiya* , S. Karthick**, M. Valarmathy***

Sandhiya, V., Karthick, S., and Valarmathy, M. (2013). A Survey Of New Reconfigurable Architectures For Implementing FIR Filters With Low Complexity. i-manager’s Journal on Electronics Engineering, 4(1), 29-39. https://doi.org/10.26634/jele.4.1.2513

Abstract

References

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A 3 GHz 2V Analog PLL at 0.18um CMOS Technology

N. K. Kaphungkui* **

Abstract

References

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S. B. Siddique* , T. M. Faruqi, B.C. Sarkar*, Mahmudul Hasan****

, , Electronics and Electrical Engineering.

****Assistant Professor, Electronics and Communication Engineering, University of Information Technology and Sciences, Dhaka 1212, Bangladesh.

* ME (Applied Electronics), Jay shriram group of institutions, Anna University, Coimbatore

** Assistant Professor (ECE), Jay shriram group of institutions, Anna University, Coimbatore

Hirald Dwaraka Praveena* , 0, N. Padmaja*

* Asst. Professor, Dept of ECE, Sree Vidyanikethan Engineering College, Tirupati.

** Professor, Dept of ECE, Sree Vidyanikethan Engineering College, Tirupati.

V. Sandhiya* , S. Karthick, M. Valarmathy*