i-manager Publications

i-manager's Journal on Electronics Engineering (JELE)

Current Issue Vol. 15 Issue 1

Most Cited

Volume 2 Issue 4 June - August 2012

Research Paper

Disturbance Rejection of Nanopositioner Using Internal Model Control

Sheilza Aggarwal * , Maneesha Garg, A. Swarup*

* Assistant Professor, Department of Electronics.

Assistant Professor, Department of Humanities and Applied Science, YMCA University of Science and Technology, India.

* Professor, Department of Electrical, National Institute of Technology, Kurukshetra, India.

Sheilza Aggarwal , Maneesha Garg and Akhilesh Swarup (2012). Disturbance Rejection of Nanopositioner Using Internal Model Control. i-manager’s Journal on Electronics Engineering, 2(4), 1-7. https://doi.org/10.26634/jele.2.4.1896

Abstract

Nanopositioning, the precise control and manipulation of devices and materials at nanoscale, plays an important role in all applications of nanotechnology. Nanopositioners are designed to move objects over a small range with a resolution down to a fraction of an atomic diameter. The primary objectives of nanopositioners include fast response with very little or no overshoot, large travel range, very high resolution, extremely high precision and high bandwidth. Performance characteristics of the system can be improved by the use of feedback controller. Complexity of controller depends upon model of the plant/process and objectives of the control system. The primary objectives of control system are to obtain fast and accurate set point tracking as well as efficient disturbances rejection. The Internal model control (IMC) structure is a suitable control system for satisfying these objectives. This paper presents the identification of nanopositioning device and analyzes its open loop behavior. The IMC scheme is implemented on non-minimum phase nanopositioning devices and is verified for set point changes and disturbance rejection. The proposed control scheme possesses good robustness against set point changes and disturbance rejection. In this paper, performance specifications of nanopositioning system with IMC structure are also compared with traditional PID controller tuning algorithms. Results simulated on MATLAB demonstrate its effectiveness and versatility for precise positioning.

References

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[2]. Kourosh kalanter-Zadeh, (2008). Benjamin Fry, “Nanotechnology- Enabled Sensor”, Springer.

[3]. B. Bhushan (2004). “Springer Handbook on nanotechnology” Berlin Germany Springer.

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[5]. K. K Leang, Q. Zou and S. Devasia (2009). “Feedforward Control of Piezoactuators in Atomic Force Microscope System” Asian Journal of Control, Vol 29 No. 1 pp 72-80.

[6]. S.M. Salapaka and M.V. Salapaka (2008). “Scanning Probe Microscope” IEEE Control System Magazine, Vol 28 No. 2, pp 65-83.

[7]. Devasia S. et al. (2007). “IEEE Transaction on Control System Technology”. “A Survey of Control Issues in Nanopositioning” . Vol 15 (5), pp 802-823.

[8]. Thomas R Hicks, Ying Xu, (1997). “The Nanopositioning Book”, Queensgate Instruments ltd.

[9]. A. A Tseng, S. Jou, A. Notargiacomo and T.C. Chen (2008) . “ Recent Development in tip based Nanofabrication and its roadmap” Journal of Nanoscience and Nanotechnology, Vol. 8, pp 2167- 2186.

[10]. B. Potsaid, J.T Wen, M. Unrath, D. watt and M. Alpay, (2007). “High Performance Motion tracking control for electronic manufacturing” Journal of Dynamic System, Measurement and Control, Vol .129, pp 767-776.

[11]. A. Ferreira and C. Mavroidis, (2006). “Virtual Reality and haptics for nanorobotics” IEEE Robot Automation Magazine, Vol. 13 No.3 pp 78-92.

[12]. Huzefa Shakir, Won-Jong kim (2007). “Multiscale control for nanoprecision positioning systems with large throughput ” IEEE Transaction on Control System Technology, Vol 15, No. 5 Sep.

[13]. S. Sebastian and S.M. Salapaka, (2005). “Design methodology for robust nanopositioning” IEEE Transaction on Control System Technology, Vol. 13, No. 6.

[14]. G. schitter, K.J. astrom,B. Demartiny, P.J. Thurner, K.L. turner, (2007). “Design and modeling of high speed AFM scanner” IEEE Transaction on Control System Technology, Vol. 15, No. 5.

[15]. K.K leang and A.J fleming, (2009). “High speed serial- kinematics AFM scanner: design and derive consideration”, Asian Journal of Control, Vol. 11, No.2.

[16]. Timothy Chang and Xuemei Sun, (2006). “Analysis and control of monolithic piezo-electric nano- actuator” IEEE Transaction on Control System Technology, Vol.9, No.1.

[17]. Sheilza jain, Maneesha garg, Akhilesh Swarup, (2011). “Identification and Performance improvement of nanopositioning devices” International Journal of Applied Engineering Research, Vol. 6, No. 5, pp 627-631.

[18]. S.O. Moheimani, (2008). “accurate and fast nanopositioning with piezoelectric tube scanner: Emerging trend and challenges”, Review of Scientific Instruments, Vol. 79, No.7.

[19]. G. schitter and A. stemmer, (2004). “ Identification and open loop tracking control of piezoelectric tube scanner for high speed scanning probe microscopy”, IEEE Transaction on Control System Technology, Vol.12, No. 3.

[20]. Andrew J. Fleming (2010). “Nanopositioning system with force feedback for high performance tracking and vibration control” IEEE Transaction on Mechatronics, Vol 15, No. 3, June.

[21]. D. croft and S. Devasia (2001). “Creep, Hysteresis and vibration compensation for piezoactuators: atomic force miscroscopy application” ASME Journal of Dynamic System and Control, Vol. 123, No. 1 pp 35-42.

[22]. A. Sebastian, S.M. Salapaka, (2005). “Design methodology for robust nanopositioning” IEEE Transaction on Control System Technology, Vol. 13, No. 6 , pp 868-876.

[23]. Qingsong Xu, and Yangmin Li, (2010). “Precise Tracking Control of a Piezoactuated Micropositioning Stage Based on Modified Prandtl-Ishlinskii Hysteresis Model”, 6th Annual IEEE Conference on Automation Science and Engineering, pp 692-697.

[24]. S. Salapaka, A. Sebastian, J.P. Cleveland and M.V. Salapaka (2002). “High Bandwidth nanopositioner: A robust control approach” Review Scientific Instruments, Vol. 73 No. 9, pp 3232-3241.

[25]. Garcia, M. Morari (1982). “Internal model control 1: A unifying Review and some new results”, Industrial Engineering Chemical Process Design and Development. Vol.21, pp 308-323.

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[28]. Seaks R, Murray J. (1981). “Feedback System Design: The tracking and Disturbance Rejection Problem” IEEE Transaction on Automatic Control, Vol 26, pp 203-217.

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Research Paper

Controller Design for Automated Drug Delivery Unit

Vipeesh P.* **

* Research Scholar, Karpagam University, Coimbatore, India.

** Principal, Tejaa Shakti Institute of Technology for Women, Coimbatore, India.

Vipeesh. P and N.J.R.Muniraj (2012). Controller Design for Automated Drug Delivery Unit. i-manager’s Journal on Electronics Engineering, 2(4), 8-13. https://doi.org/10.26634/jele.2.4.1898

Abstract

Disease classification and drug diffusion are the two major tasks that have to be performed by automated drug delivery unit. Both these operations have to be performed with utmost care and the performance of the system should be reliable and reproducible. The electrical signals that are produced by the sensor array network, that indicate the concentration of analyte solution based on the kind of disease being detected, is used as the input to the classification problem. The developed model is used for classification cancer data obtained from the sensor array network. In this paper design of controller for drug diffusion is also presented. Both the novel algorithm based expert system and the controller logic for drug diffusion to measure and analyze the real time performance of the system. A detailed discussion on the design, modelling and implementation of the expert system and drug delivery unit is presented.

References

[1]. P. Vipeesh and N.J.R. Muniraj, (2011). “Development and validation of Matlab models for nanowire sensors”, Communications in Computer and Information Science, (2011), pp. 270–283. © Springer-Verlag Berlin Heidelberg.

[2]. P. Vipeesh and N.J.R. Muniraj, “Design and modelling PSA detection for prostate cancer using 8 x 8 sensor array”, Int. J. Biomedical Engineering and Technology, accepted.

[3]. Rajendra Katti, (l994). “A Modified Booth Algorithm for High Radix Fixed-point Multiplication”, IEEE Transactions On Very Large Scale Integration (VLSI) Systems, Vol 2, No 1, December.

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[6]. Shyh-Jye Jou, Chang-Yu Chen, En-Chung and Chau- Chin Su (2000). “A Pipeline Multiplier-Accumulator Using a High Speed Low-Power Static and Dynamic Full Adder” Journal of Solid State Circuits, Vol 32, No-1, January.

[7]. C. S. Wallace, (1964). “A suggestion for fast multipliers,” IEEE Trans. Electron. Computers, Vol. 13, pp. 14-17, Feb.

[8]. M. R. Santoro and M. A. Horowitz, (1989). “SPIM: a pipelined 64×64- bit iterative multiplier,” IEEE J. Solid-State Circuits, Vol.24, No. 2, pp. 487-493, Apr.

[9]. B-I. Park, I-C. Park, and C-M. Kyung, (1999). “A regular layout structured multiplier based on weighted carry-save adders,” Proc. IEEE International Conference on Computer Design, pp.243-248, Oct.

[10]. J. Yuan and C. Svensson, (1989). “High-speed CMOS circuit technique,” IEEE J. Solid-State Circuits, Vol. 24, No. 1, pp. 62- 70, Feb.

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[13]. N. Ohkubo, et al., (1995). “A 4.4ns CMOS 54×54-b multiplier using pass-transistor multiplexer,” IEEE J. Solid- State Circuits, Vol. 30, No. 3, pp. 251-257, Mar.

[14]. KiamalZ. Pekmestzi, (1999). “Multiplexer-Based Array Multipliers”, IEEE Transactions on Computers, Vol. 48, No. 1, January.

[15]. PedramMokrian, (2003). “A Reconfigurable Digital Multiplier Architecture” A Master's Thesis, Department of Electrical and Computer Engineering, University of Windsor, April.

[16]. Gary W. Bewick, (1994). “Fast Multiplication: Algorithms and Implementation”, A Ph.D Dissertation, Stanford University.

[17]. D. Radhakrishnan, (1999). “Low Voltage CMOS Full Adder Cells,”Electronics Letters, Vol. 35, pp. 1792-94, October.

[18] . Anant Yogeshwar Chitari, (2000). “VLSI Architecture for a 16-bit Multiply-Accumulator (MAC) Operating in Multiplication Time”, A Master's Thesis, Department of Electrical Engineering, Texas A&M University –Kingsville, May.

[19]. Behrooz Parhami, (2000). “Computer Arithmetic: Algorithms and Hardware Designs”, Oxford University Press, New York.

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Research Paper

Analysis of VFTOS across Insulating Flange of 420 Kv Gis

A. Raghu Ram*

* Associate Professor, Department of Electrical and Electronics Engineering, J.N.T.U.H College of Engineering, Hyderabad, India.

** Manager, Balanagar, Hyderabad, India.

A. Raghu Ram and M. Mohana Rao (2012). Analysis of VFTOS across Insulating Flange of 420 KV GIS. i-manager’s Journal on Electronics Engineering, 2(4), 14-20. https://doi.org/10.26634/jele.2.4.1899

Abstract

In gas insulated substations(GIS) very fast transient overvoltages(VFTO) are generated due to disconnector switching operations. Disconnector switches are primarily used to isolate the operating sections of HV installation from each other as a safety measure. Very fast transient over voltages at an insulating flange are generated due to propogation of VFTOs on the conductor of a gas bus in GIS.Genaration of VFTOs causes sparkovers across insulating flange of high pressure oil filled cable/GIS interface.The ionised path formed by the sparkovers create low impedance path for power frequency fault current, resulting in flange damage with serious consequences.This paper deals wih the generation of VFTOs across insulating flange and their suppression using shunting bars and capacitors for providing protection have been analyzed and reported using MATLAB 7.0.

References

[1]. Amir Mansour miri and Zlatan Stojkovic (2001). ”Transient electromagnetic phenomena in the secondary circuits of voltage and current Transformers in GIS (Measurements and Calculations)”. IEEE Transaction on Power Delivery, No 4 October.

[2]. Dr. M. Mohan Rao, M. Joy Thomas and B.P. Singh (2002). “Frequency spectrum analysis of fast transient currents (FTC) due to switching operations in 245KV GIS” IEEE Transactions on Power Delivery in year.

[4]. YoshibuminYamagata, Yasuhiko Nakada, of Tokyo electrical power Co., Japan, (1999). “Very fast transients in 1000KV Gas Insulated Switchgear” IEEE Transactions on Power Delivery in the year.

[5]. N. Fujimoto, S.J. Croall and S.M. Foty (1988). “Techniques for the Protection of Gas Insulated Substation to Cable Interfaces” IEEE Transactions on Power Delivery, Volume 3, No 4, October.

[6]. Ogawa S., Hanginomori E., (1986). 'Estimation of Restriking Transient overvoltage on Disconnecting Switch for GIS', IEEE Tans. P.S., Vol. PWRD-1, No.2, PP.95-101.

[7]. Witzman R., (1987). 'Fast Transients in Gas Insulated substations – Modelling of Different GIS components', Fifth ISH, Braunschweig, paper No. 12.06.

[8]. Yanabu S., (1990). 'Estimate of Fast Transient over Voltage in Gas Insulated Substation', IEEE Trans. P.D, Vol.5, No.4, pp.1875-1881.

[9]. Alvinson et al., (1988). 'Very fast Transient Phenomena associated with Gas Insulated Substations', CIGRE – Report 33-13.

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Research Paper

Design and implementation of EEG Measuring System

Safaa S. Mahdi* **

* Lecturer, Department of Electronics and Communications Engineering.

** Department of Medical Engineering, Nahrain University.

Safaa S. Mahdi and Mahir R. Alhajjaj (2012). Design and Implementation of EEG Measuring System. i-manager’s Journal on Electronics Engineering, 2(4), 21-26. https://doi.org/10.26634/jele.2.4.1902

Abstract

Electroencephalograph (EEG) is a technique commonly used in medical and research fields to record the electrical activities of the brain. The EEG signals are recorded from the surface of the scalp metallic electrodes. The EEG signals are within the range of (0.5-50µV), the raw signals are originated from different areas of the brain. The locations of these electrodes on the scalp are specified according to the 10-20 international system. Measuring the EEG signals is usually difficult due to small signal magnitude of the EEG signals and large DC offset voltage incorporated with the measuring process. The DC-offset in EEG signal is a result of many factors, like electrode-skin interface, amplifier input bias current mismatch, input impedance, offset voltage, and voltage drift with temperature and aging. The signal is amplified in two stages and digitized using a 24-bit analog to digital convertor (ADC). The DC-offset was treated using auto-zeroing technique, along with the use of high precision electronic components. The theoretical design was first simulated using TINA-TI software, then the PCB's were designed using Eagle software, and implemented experimentally. EEG signals were acquired and recorded for different people and it seems satisfactory for the diagnosis by doctors.

References

[1]. Daniel Novák, LenkaLhotská, Vladimír Eck, Milan Sorf, (2004). EEG and VEP Signal Processing, Department of Cybernetics, Czech Technical University in Prague, Czech Republic.

[2]. Adolf Faller, Michael Schünke and Gabriele Schünke, (2004). The Human Body, an Introduction to Structure and Function, Thieme.

[3]. SaeidSanei and J.A. Chambers, (2007). EEG Signal Processing, John Wiley & Sons Ltd.

[4]. AD8571/AD8572/AD8574 datasheet, Analog Devices, Inc., 1999-2008.

[5]. John G. (2000). Webster, The Measurement, Instrumentation, and Sensors Handbook, CRC press LLC.

[6]. Christian C. Enz and GaborC. Temes, (1996). Circuit Techniques for Reducing the Effects of Op-Amp Imper fections: Autozeroing, Correlated Double Sampling, and Chopper Stabilization, Proceeding of the IEEE, Vol. 84, No. 11. November.

[7]. Demystifying Delta-Sigma ADCs, Application notes, Maxim Integrated Products, 2003.

[8]. M. Teplan, (2002). Fundamentals of EEG Measurement, Measurement Science Review, Volume 2, Section 2.

[9]. Ramaswamy Palaniappan, (2010). Biological Signal Analysis, Ramaswamy Palaniappan & Ventus publishing ApS.

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Research Paper

Design of CNTFET Based Logic Gates for Ultra Low Power Applications

V. Saravanan* , Kannan .V**

* Research Scholar, Sathyabama University, Tamilnadu, India.

** Principal, Jeppiaar Institute of Technology, Tamilnadu, India

V. Saravanan and V. Kannan (2012). Design of CNTFET based Logic Gates for Ultra Low Power Applications. i-manager’s Journal on Electronics Engineering, 2(4), 27-31. https://doi.org/10.26634/jele.2.4.1905

Abstract

This paper proposes the design of logic gates for Ultra Low Power Applications. The logic gate has been designed In 18 Nm technology. In this paper Carbon Nano-Tube Field Effect Transistors (CNTFET) are introduced for designing the digital circuits. This paper presents the performance analysis of Carbon Nanotube Field Effect Transistor (CNTFET), structure, types of the new Nano Device, operation, and various gate circuit design using CNTFET. Results of the proposed design are compared with CMOS based gates. All the simulations are done in hspice.

References

[1]. Appenzeller J (2008). “Carbon Nanotubes for High- Performance Electronics Progress and Prospect ”, Proceedings of the IEEE, Vol. 96, No. 2, pp. 201-211.

[2]. Postma H, Teepen T, Yao Z et al. (2001). “Carbon Nanotube Single-Electron Transistors at Room Temperature”, Science, Vol. 293, No. 5527, pp. 76-79.

[3]. Kurt A. Moen (2010). “Evaluating the Influence of Various Body-Contacting Schemes on Single Event Transientsin 45-nm SOI CMOS” IEEE Transactions on Nuclear Science, Vol. 57, No. 6, pp 3366 – 3372.

[4]. Kyung Ki Kim (2010). “On-Chip Aging Sensor Circuits for Reliable Nanometer MOSFET Digital Circuits” IEEE Transactions on Circuits and Systems, Vol. 57, No. 10, pp 798 – 802.

[5]. Davide Ponton (2009). “Design of Ultra-Wideband Low-Noise Amplifiers in 45-nm CMOS Technology: Comparison Between Planar Bulk and SOI FinFET Devices”, IEEE Transactions on Circuits and Systems, Vol. 56, No. 5, pp 920 – 932.

[6]. Radosavljevic, M. et al. (2003). “Drain Voltage Scaling in Carbon Nanotube Transistors” Appl. Phys. Lett., Vol. 83, No. 12, p. 2435-2437.

[7]. Pecchia, A. et al. (2003). “Electronic Transport Properties of Molecular Devices”, Physical Review Letters, Vol. 19,pp. 139-144.

[8]. Kyung Ki Kim, Yong-Bin Kim, Ken Choi (2011).“Hybrid CMOS and CNFET Power Gating in Ultralow Voltage Design” IEEE Transactions on Nanotechnology, Vol. 10, No. 6, Pp 1439-1448.

[9]. Li J, Zhang Q, Yan Y et al. (2007). “Fabrication of Carbon Nanotube Field-Effect Transistors by Fluidic Alignment Technique”, IEEE Transactions on Nano- Technology, Vol. 6, No. 4, pp. 481-484.

[10]. Bachtold A, Hadley P, Nakanishi T and Dekker (2001). “Logic Circuits with Carbon Nanotube Transistors”, Science, Vol. 294, No. 9, pp. 1317-1320.

[11]. Chen Z, Appenzeller J, Lin Y-M et al. (2006). “An Integrated Logic Circuit Assembled on a Single Carbon Nanotube”, Science, Vol. 311, No. 5768, p. 1735.

[12]. Rahman A, Jing Guo, Datta S and Lundstrom M S. (2003). “Theor y of Ballistic Nanotransistors”, IEEE Transactions on Electron Devices, Vol. 50, No. 10, pp. 1853-1864.

[13]. Raychowdhury, A. and Roy, K. (2005), “Carbon Nanotube-Based Voltage-Mode Multiple-Valued Logic Design”, IEEE Trans. Nanotechnology, Vol. 4, No. 2, pp. 168-179.

[14]. Han, J. and Jonker, P. (2002). “A System Architecture Solution for Unreliable Nanoelectronic Devices”, IEEE Trans. Nanotechnology, Vol.1, pp. 201-208.

[15]. Heinze S et al. (2002). “Carbon Nanotubes as Schottky Barrier Transistors”, Physical Review Letters, Vol. 89.

[16]. Ian O'Connor, Junchen Liu, et al (2007). “CNTFET Modeling and Reconfigurable Logic-Circuit Design” IEEE Transactions on Circuits and Systems, Vol. 54, No. 11, pp 2365-2379.

[17]. Khairul Alam, Roger Lake, l (2007). “Role of Doping in Carbon Nanotube Transistors With Source/Drain Underlaps” IEEE Transactions on Nanotechnology, Vol. 6.

[18]. Youngki Yoon, James Fodor, and Jing Guo, (2008). “A Computational Study of Vertical Partial-Gate Carbon- Nanotube FETs” IEEE Transactions on Electron Devices, Vol.55, No. 1.

[19]. J. Liu, I. O'Connor, D. Navarro, F. Gaffiot (2007). “Design of a Novel CNTFET- based Reconfigurable Logic Gate” IEEE Computer Society Annual Symposium on VLSI(ISVLSI'07).

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[21]. Deji Akinwande, Yoshio Nishi,and H.S. Philip Wong, (2008). “ An Analytical Derivation of the Density of States, Effective Mass, and Carrier Density for Achiral Carbon Nanotubes” IEEE Transactions On Electron Devices, Vol. 55, No. 1, Pp 289 – 297.

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i-manager's Journal on Electronics Engineering (JELE)

Current Issue Vol. 15 Issue 1

Most Read

Most Cited

Volume 2 Issue 4 June - August 2012

Disturbance Rejection of Nanopositioner Using Internal Model Control

Sheilza Aggarwal * , Maneesha Garg**, A. Swarup***

* Assistant Professor, Department of Electronics. ** Assistant Professor, Department of Humanities and Applied Science, YMCA University of Science and Technology, India. *** Professor, Department of Electrical, National Institute of Technology, Kurukshetra, India.

Sheilza Aggarwal , Maneesha Garg and Akhilesh Swarup (2012). Disturbance Rejection of Nanopositioner Using Internal Model Control. i-manager’s Journal on Electronics Engineering, 2(4), 1-7. https://doi.org/10.26634/jele.2.4.1896

Abstract

References

Full Article (HTML)

Pdf

Controller Design for Automated Drug Delivery Unit

Vipeesh P.* **

* Research Scholar, Karpagam University, Coimbatore, India. ** Principal, Tejaa Shakti Institute of Technology for Women, Coimbatore, India.

Vipeesh. P and N.J.R.Muniraj (2012). Controller Design for Automated Drug Delivery Unit. i-manager’s Journal on Electronics Engineering, 2(4), 8-13. https://doi.org/10.26634/jele.2.4.1898

Abstract

References

Full Article (HTML)

Pdf

Analysis of VFTOS across Insulating Flange of 420 Kv Gis

A. Raghu Ram*

* Associate Professor, Department of Electrical and Electronics Engineering, J.N.T.U.H College of Engineering, Hyderabad, India. ** Manager, Balanagar, Hyderabad, India.

A. Raghu Ram and M. Mohana Rao (2012). Analysis of VFTOS across Insulating Flange of 420 KV GIS. i-manager’s Journal on Electronics Engineering, 2(4), 14-20. https://doi.org/10.26634/jele.2.4.1899

Abstract

References

Full Article (HTML)

Pdf

Design and implementation of EEG Measuring System

Safaa S. Mahdi* **

* Lecturer, Department of Electronics and Communications Engineering. ** Department of Medical Engineering, Nahrain University.

Safaa S. Mahdi and Mahir R. Alhajjaj (2012). Design and Implementation of EEG Measuring System. i-manager’s Journal on Electronics Engineering, 2(4), 21-26. https://doi.org/10.26634/jele.2.4.1902

Abstract

References

Full Article (HTML)

Pdf

Design of CNTFET Based Logic Gates for Ultra Low Power Applications

V. Saravanan* , Kannan .V**

* Research Scholar, Sathyabama University, Tamilnadu, India. ** Principal, Jeppiaar Institute of Technology, Tamilnadu, India

V. Saravanan and V. Kannan (2012). Design of CNTFET based Logic Gates for Ultra Low Power Applications. i-manager’s Journal on Electronics Engineering, 2(4), 27-31. https://doi.org/10.26634/jele.2.4.1905

Abstract

References

Full Article (HTML)

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Sheilza Aggarwal * , Maneesha Garg, A. Swarup*

* Assistant Professor, Department of Electronics.

Assistant Professor, Department of Humanities and Applied Science, YMCA University of Science and Technology, India.

* Professor, Department of Electrical, National Institute of Technology, Kurukshetra, India.

* Research Scholar, Karpagam University, Coimbatore, India.

** Principal, Tejaa Shakti Institute of Technology for Women, Coimbatore, India.

* Associate Professor, Department of Electrical and Electronics Engineering, J.N.T.U.H College of Engineering, Hyderabad, India.

** Manager, Balanagar, Hyderabad, India.

* Lecturer, Department of Electronics and Communications Engineering.

** Department of Medical Engineering, Nahrain University.

* Research Scholar, Sathyabama University, Tamilnadu, India.

** Principal, Jeppiaar Institute of Technology, Tamilnadu, India