Abstract

This paper presents an improved FPGA based stator flux and torque estimators for direct torque control of induction motor drive. In voltage model -based of stator flux estimation, a low pass (LP) filter is normally used instead of a pure integrator to avoid integration drift problem due to DC off-set, noise and measurement error present in the back electromotive force (emf).In steady state condition, the LP filter estimator will degrade the performance and efficiency of the induction motor drive system since it introduced magnitude and phase errors. A simple method is proposed to improve the steady state performances of the drive system. MATLAB/SIMULINK and Xilinx System Generator tools are used to model and view the functionality of the proposed system.

Abstract

The fast emerging highly-integrated multimedia devices require complex video/image processing tasks leading to a very challenging design process; as it demands more efficient and high processing systems. Neural networks are used in many of these imaging applications to represent the complex input-output relationships. Software implementation of these networks attain accuracy with tradeoffs between processing performance (to achieve specified frame rates, working on large image data sets), power and cost constraints. The current trends involve conventional processor being replaced by the Field programmable gate array (FPGA) systems due to their high performance when processing huge amount of data.  The goal is to design the Combinational Neural Networks (CNN) for pattern recognition using an FPGA based platform for accelerated performance. The enhancement in speed and computation from the hardware is being compared to the software (using MATLAB) model. The employment of HDL on the FPGA enables operations to be performed in parallel. Thus allowing the exploitation of the vast parallelism found in many real-world applications such as in robotics, controller free gaming and sign/gesture recognition. As a validation of the CNN hardware model a case study in pattern recognition is being explored and implemented on Xilinx Spartan 3E FPGA board. To measure the quality of learning in the trained network mean squared error is used. The processing performance of this non-linear stochastic tool is determined by comparing the HDL (parallel model) simulations with the MATLAB design (sequential model). The gain in training time and memory used for processing is also derived.

Abstract

In this paper, in order to investigation the dynamic performance of an Interline Power Flow Controller (IPFC) in enhancing the stability of a power system and in spite of being aware of the strong ability of the Particle Swarm Optimization (PSO) algorithm in finding the global optimum solution of a problem, a novel supplementary controller scheme for the IPFC is considered to be designed. With due attention to the simplicity and availability of the decentralized output feedback control methodology, it is take into account to be optimally designed using the PSO algorithm. For this purpose, the linearized Heffron-Phillips model of a Single-Machine Infinite Bus (SMIB) system is established and the Integral of Time multiplied Absolute value of Error (ITAE)  is applied as an objective function to design an output feedback controller in order to evaluate the potential of various IPFC control signals upon the power system's different operating conditions. The results in time-domain simulation analysis reveal that the designed PSO based IPFC controller tuned by the proposed objective function has an excellent capability in damping power system low frequency oscillations and enhance greatly the dynamic stability of the power systems. Moreover, through analyzing some performance indices, it is obvious that the m1 (magnitude of injected voltage) based controller is superior to the other based controller.

Abstract

This paper presents the simulation analysis of a 2.4 GHz Quadrature Voltage Controlled Oscillator (QVCO), for low-power, low-voltage applications. Cross coupled LC VCO (Inductor-Capacitor Voltage Controlled Oscillator) topology is utilized to realize QVCO. With the passive coupling achieved from the MOS transistors, power consumption is minimized while maintaining a small chip area. The variable capacitors and the inductors are designed using ANSYS and imported through DAC components in ADS (Advanced Design software). Accurate simulation of the QVCO is performed in the software environments and the results are provided. This QVCO provides quadrature signals at 2.4 GHz, achieves a peak to peak voltage of 0.65 volts with a simulated low power consumption of 5.8 mA from a power supply voltage of 0.6 volts. The simulated QVCO produces frequency tuning from 2.1 GHz to 2.60 GHz (20.83%) with a control voltage varying from 0-0.3 volts. The output power level of the QVCO is -7 dBm, with an improved predicted quality factor of 60 and a phase noise of -134 dBc/Hz, 1MHz far from the carrier frequency.

Abstract

In this paper the system for simulation, measurement and processing in graphical user interface implementation is presented. The received signal from the simulation is compared to that of an actual measurement in the time domain. The comparison of simulated, experimental data clearly shows that acoustic wave propagation can be modelled. The feasibility has been demonstrated in an ultrasound transducer setup for material property investigations. The results of simulation are compared to experimental measurements. Results obtained fit some much with those found in experiment and show the validity of the used model. The simulation tool therefore provides a way to predict the received signal before anything is built. Furthermore, the use of an ultrasonic simulation package allows for the development of the associated electronics to amplify and process the received ultrasonic signals. Such a virtual design and testing procedure not only can save us time and money, but also provide better understanding on design failures and allow us to modify designs more efficiently and economically.

Abstract

This paper proposes a new LBP with ENI approach to extract local image features for the purpose of Images classification.  This new LBP method introduces the notion of ENI (the abbreviation for “edge pixels, noisy pixels and interior pixels”) which denotes the number of homogeneous pixels in a local neighborhood, and is significantly different for edge pixels, noisy pixels and interior pixels. We redefine the controlling speed function and the controlling fidelity function to depend on ENI. According to our controlling function, the diffusion and fidelity process at edge pixels, noisy pixels and interior pixels can be selectively carried out. Further, a class of second-order improved, edge-preserving denoising method is applied based on the controlling function in order to deal with random-valued impulse noise reliably. The experimental results on representative image databases show that the proposed method is robust to noise and can achieve significant improvement in terms of the obtained classification accuracy in comparison to the LBP method and it’s extensions.

Abstract

Today's military voice radio systems were not designed to provide the bandwidth required by today’s multimedia data flows, particularly video. Worldwide, armies are looking for broadband radio access solutions to their tactical needs, and are testing Commercial-Off-The-Shelf (COTS) solutions such as WiMAX. Wireless Sensor Networks which is a type of wireless network consist of small nodes with capabilities of sensing physical or environmental conditions, processing related data and send information wirelessly. These WSN Dense deployments of disposable and low-cost sensor nodes make WSN concept beneficial for battle fields. In Military Applications, the literature discusses WSNs usage for tracking missiles and other possibilities include using WSNs as a military monitoring network for surveillance purposes to monitor large areas against intruders and send alerts and information about intruders using NS2.  Some military applications of WSNs are:

Monitoring friendly forces, equipment and ammunition.

Battlefield surveillance

Exploration of opposing forces and terrain

Targeting

Battle damage assessment

Nuclear, biological and chemical attack detection

Abstract

This paper presents an algorithm and architecture that facilitate the area-efficient evaluation of arithmetic expressions using deeply pipelined floating-point cores. Due to technological advances, it has become possible to implement ?oating point cores on FPGAs in an effort to provide hardware acceleration for the myriad applications that require high performance ?oating-point arithmetic. However, in order to achieve a high clock rate, these ?oating-point cores must be deeply pipelined. Due to this deep pipelining and the complexity of ?oating-point arithmetic, ?oating-point cores use a great deal of the FPGA’s area. It is thus important to use as few ?oating-point cores in architecture as possible. However, the deep pipelining makes it difficult to reuse the same ?oating-point core for a series of ?oating-point computations that are dependent upon one another. Our Results show the correctness of the algorithm and that the performance achieved is far superior to that of other techniques. Beyond area efficiency, this design has several benefits, including high throughput and a low memory space requirement. Because it only needs to receive one input per clock cycle, it also has a low I/O bandwidth requirement. Because of the low area and the low bandwidth requirement, it is possible to implement multiple copies of the architecture in a single design.