i-manager Publications

Volume 13 Issue 3 April - June 2023

Research Paper

Design and Analysis of Ternary Delay Flip-Flop Implemented with Carbon Nanotube Field Effect Transistor

Pradeep Singh Yadav* , Chinmay Chandrakar, Anil Kumar Sahu*

* Department of Electronics and Communication, Sagar Institute of Science and Technology, Bhopal, Madhya Pradesh, India.

Shri Shankaracharya Technical Campus, Bhilai, India.

* Bharat Institute of Engineering and Technology, Hyderabad, India.

Yadav, P. S., Chandrakar, C., and Sahu, A. K. (2023). Design and Analysis of Ternary Delay Flip-Flop Implemented with Carbon Nanotube Field Effect Transistor. i-manager’s Journal on Electronics Engineering, 13(3), 1-10. https://doi.org/10.26634/jele.13.3.19808

Abstract

Flip-flops serve as fundamental memory storage elements in digital circuits, and their efficiency significantly affects overall circuit performance. The aim of this study is to create a D flip-flop based on ternary logic and evaluate its performance in comparison to flip-flops that have already been designed. The proposed D flip-flop design leverages Carbon Nanotube Field Effect Transistors (CNTFETs). CNTFETs offer unique properties that can enhance the speed and power efficiency of flip-flop design. To evaluate the performance of the proposed design, it was simulated using the HSPICE simulator with a 32 nm Stanford CNTFET model. The simulation parameters include a power supply voltage of 0.9 volts and an operating frequency of 1 GHz. These specific settings allow researchers to analyze the behavior and performance of flip-flops under realistic operating conditions. By comparing the simulation results of the proposed D flipflop with the performance of previously designed flip-flops, the improvements are assessed in terms of the speed and power consumption. The simulation results provide valuable insights into the efficiency, reliability, and responsiveness of the proposed design. The findings of this research contribute to the advancement of digital circuit design by introducing a novel D flip-flop based on ternary logic and CNTFET technology. The goal is to enhance the overall performance efficiency of digital circuits, particularly in applications where D flip-flops are used as building blocks such as shift registers.

References

[1]. Dadashi, M., Manochehri, K., & Pourmozafari, S. (2016). Low power CNTFET based 4-2 and 5-2 compressor. In Proceedings of the 4th International Conference on Applied Researches in Computer Engineering and Signal Processing.

[2]. Gavaber, M. D., Kalantari, K. M., & Pourmozafari, S. (2016, December). Design of high speed and low power D Flip-Flop by CNTFET technology. In 3rd International Conference on Knowledge-Based Engineering and Innovation, Tehran, Iran (pp. 1-5).

[3]. Joshi, P., Khandelwal, S., & Akashe, S. (2015, February). Implementation of Low Power Flip Flop Design in Nanometer Regime. In 2015 Fifth International Conference on Advanced Computing & Communication Technologies (pp. 252-256). IEEE.

[4]. Kabir, M. A., Nandy, T., Haque, M. A., Dutta, A., & Mahmood, Z. H. (2014). Performance analysis of CNTFET and MOSFET focusing channel length, carrier mobility and ballistic conduction in high speed switching. International Journal of Advances in Materials Science and Engineering (IJAMSE), 3(3), 1-11.

[5]. Liao, K., Cui, X., Liao, N., & Wang, T. (2014, October). Design of D flip-flops with low power-delay product based on FinFET. In 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) (pp. 1-3). IEEE.

[6]. Lin, S., Kim, Y. B., & Lombardi, F. (2009). CNTFET-based design of ternary logic gates and arithmetic circuits. IEEE Transactions on Nanotechnology, 10(2), 217-225.

[7]. Marani, R., Gelao, G., & Perri, A. G. (2013). Modelling of Carbon Nanotube Field Effect Transistors oriented to SPICE software for A/D circuit design. Microelectronics Journal, 44(1), 33-38.

[8]. Murotiya, S. L., & Gupta, A. (2013, September). Performance evaluation of CNTFET based dynamic dual edge triggered register. In 2013 International Conference on Advanced Electronic Systems (ICAES) (pp. 180-183). IEEE.

[9]. Ravi, T., & Kannan, V. (2012, December). Effect of Ntype cntfet on double edge triggered D flip-flop based PISO shift register. In 2012 International Conference on Emerging Trends in Science, Engineering and Technology (INCOSET) (pp. 344-349). IEEE.

[10]. Shahrom, E., & Hosseini, S. A. (2018). A new low power multiplexer based ternary multiplier using CNTFETs. AEU-International Journal of Electronics and Communications, 93, 191-207.

[11]. Sharma, T., & Sharma, D. (2022, February). Design of ternary flip-flop cells using Maximum/Minimum logic operators in carbon nanotube technology. In 2022 Second International Conference on Artificial Intelligence and Smart Energy (ICAIS) (pp. 1693-1697). IEEE.

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Research Paper

The Design of a Low-Power 4-Bit Barrel Shifter for a Current Steering DAC using Optimized Multiplexers in 65 nm Technology

Ashok Kumar Adepu* , Balaji Narayanam**

*-** Department of Electronics and Communication Engineering, Jawaharlal Nehru Technological University, Kakinada, Andhra Pradesh, India.

Adepu, A. K., and Narayanam, B. (2023). The Design of a Low-Power 4-Bit Barrel Shifter for a Current Steering DAC using Optimized Multiplexers in 65 nm Technology. i-manager’s Journal on Electronics Engineering, 13(3), 11-22. https://doi.org/10.26634/jele.13.3.19829

Abstract

CMOS technology scaling has paved the way for a faster and more complex integration. Low-power techniques have become crucial because of the demand for low power consumption and high speed. The main objective of this research is to utilize low-power techniques to implement a 4-bit barrel shifter that can shift or rotate data using any number of bits within a single cycle. Gate Diffusion Input (GDI), modified GDI, and full-swing GDI logic have been employed to implement a 2:1 multiplexer, among which the modified GDI-based multiplexer stands out because of its minimal power consumption. Consequently, a 4-bit barrel shifter is implemented using a modified GDI-based multiplier. All designs and simulations were performed using the Cadence Virtuoso tool in UMC 65 nm technology. This technology enables the accurate analysis and assessment of the designed barrel shifter, considering the characteristics and limitations of the 65 nm process. This study focused on leveraging low-power techniques to implement a 4-bit barrel shifter to address the industry's demand for power-efficient solutions. The modified GDI-based multiplexer is a promising choice that provides a balance between low power consumption and high performance. The use of advanced design tools and selected technology further ensures accurate simulations and evaluations of the proposed design.

References

[1]. Adarsh, C. S. D., Lakshmi, T. V., & Kamaraju, M. (2017, April). Implementation and comparative analysis of double gate low power multiplexers using dynamic logic styles. In 2017 International conference of Electronics, Communication and Aerospace Technology (ICECA), 2, 323-328. IEEE.

[2]. Ahmed, M. A., & Abdelghany, M. A. (2018, February). Low power 4-bit arithmetic logic unit using full-swing GDI technique. In 2018 International Conference on Innovative Trends in Computer Engineering (ITCE) (pp. 193-196). IEEE.

[3]. Anugraha, R. V., Durga, D. S., & Avudaiammam, R. (2017, May). Design and performance analysis of 2:1 multiplexer using multiple logic families at 180 nm technology. In 2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) (pp. 1849-1853). IEEE.

[4]. Aradhya, H. V. R., Lakshmesha, J., & Muralidhara, K. N. (2012). Design optimization of reversible logic universal barrel shifter for low power applications. International Journal of Computer Applications, 40(15), 26-34.

[5]. Badry, O. A., & Abdelghany, M. A. (2018, February). Low power 1-Bit full adder using Full-Swing gate diffusion input technique. In 2018 International Conference on Innovative Trends in Computer Engineering (ITCE) (pp. 205-208). IEEE.

[6]. Hashmi, I., & Babu, H. M. H. (2010, January). An efficient design of a reversible barrel shifter. In 2010 23rd International Conference on VLSI Design (pp. 93-98). IEEE.

[7]. Koppala, A., & Mallavarapu, R. B. (2017). A study on ALU design using dynamic CMOS logic families. Emperor International Journal of Finance and Management Research (pp. 157-163).

[8]. Kumar, S. R., & Praveen, N. V. (2015). Design of highspeed modified-GDI based carry select adder. International Research Journal of Engineering and Technology (IRJET), 2(2), 47-50.

[9]. Mittal, P., Rawat, B., & Kumar, N. (2022). Tetra-variate scrutiny of diverse multiplexer techniques for designing a barrel shifter for low power digital circuits. Microprocessors and Microsystems, 90, 104491.

[10]. Mukherjee, B., & Ghosal, A. (2015, July). Design & study of a low power high speed full adder using GDI multiplexer. In 2015 IEEE 2nd International Conference on Recent Trends in Information Systems (ReTIS) (pp. 465-470). IEEE.

[11]. Patel, B., & Devi, M. (2019). A novel low power MUX based dynamic barrel shifter using footed diode domino logic. International Journal of Innovative Technology and Exploring Engineering (IJITEE), 8(6S3), 307-311.

[12]. Sahoo, J. S., & Rout, N. (2015). Comparative study on low power barrel shifter/rotator at 45nm technology. International Journal of Advanced Engineering and Nano Technology (IJAENT), 2(6), 11-18.

[13]. Swetha, S. (2016). Design of low power and area efficient full adder using modified gate diffusion input. International Journal of Computer Applications, 145(8), 45-47.

[14]. Swetha, S., & Begum, M. A. (2017). Design of high speed, area optimized and low power arithmetic and logic unit. Advances in Industrial Engineering and Management, 6(1), 26-31.

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Research Paper

A Miniaturized Antenna for Mobile Broad-Band/Cordless Phones/Wireless Audio Devices/ISM

Prakshep Kumar Rai* , Shambhavi M. Shukla, Chandan*, Ashutosh K. Singh****

*-**** Department of Electronics and Communication Engineering, Dr. Ram Manohar Lohia Avadh University, Ayodhya, Uttar Pradesh, India.

Rai, P. K., Shukla, S. M., Chandan, and Singh, A. K. (2023). A Miniaturized Antenna for Mobile Broad-Band/Cordless Phones/Wireless Audio Devices/ISM. i-manager’s Journal on Electronics Engineering, 13(3), 23-32. https://doi.org/10.26634/jele.13.3.19832

Abstract

This research introduces the design and simulation of a monopole antenna with a simple ground plane, specifically developed for dual-band communication. The antenna consists of a radiating patch, feed line, and ground plane, and it was fabricated on an FR-4 substrate. The operating frequency bands of the antenna cover 2.5–2.7 GHz and 3.9–4.6 GHz. By carefully selecting the dimensions, the antenna achieves resonance frequencies at 2.6 GHz and 4.2 GHz, with corresponding bandwidths of 200 MHz and 700 MHz. The research provided excellent impedance matching for the antenna, as indicated by the measured return loss (S11) values of -29.35 dB and -22.48 dB, surpassing the required criterion of S11 < -10 dB. The compact size of the antenna, measuring 12×24×1.6 mm³, makes it highly suitable for applications with space limitations. The antenna performance was extensively analyzed through simulations utilizing High-Frequency Structure Simulator (HFSS) software. The results validate its effectiveness for two specific frequency bands:2.6 GHz for mobile broadband service and 4.2 GHz for various applications such as cordless phones, wireless audio devices, and industrial, Scientific, and Medical Networks (ISM). This research lays a solid foundation for future developments in dual-band communication antennas, offering potential benefits in terms of connectivity and communication efficiency.

References

[1]. Bagci, F., Can, S., Karakaya, E., Mulazimoglu, C., Yilmaz, A. E., & Akaoglu, B. (2017, September). Optically transparent frequency selective surface for filtering 2.6 GHz LTE band. In 2017 IV International Electromagnetic Compatibility Conference (EMC Turkiye) (pp. 1-4). IEEE.

[2]. Boukarkar, A., Lin, X. Q., Jiang, Y., & Yu, Y. Q. (2016). Miniaturized single-feed multiband patch antennas. IEEE Transactions on Antennas and Propagation, 65(2), 850-854.

[3]. Chatterjee, A., Midya, M., & Mitra, M. (2017, December). Dual-band miniaturized planar inverted Fantenna for WLAN and 5G application. In 2017 IEEE Applied Electromagnetics Conference (AEMC) (pp. 1-2). IEEE.

[4]. Chou, R. Y., Wu, C. Y., & Yeh, S. H. (2007, October). Switchable printed monopole antenna with frequency diversity for WiFi/2.6 GHz WiMAX/3.5 GHz WiMAX applications. In TENCON 2007-2007 IEEE Region 10 Conference (pp. 1-3). IEEE.

[5]. Gangwar, A. K., & Alam, M. S. (2019). A miniaturized quad-band antenna with slotted patch for WiMAX/WLAN/GSM applications. AEU-International Journal of Electronics and Communications, 112, 152911.

[6]. Gharode, D., Nella, A., & Rajagopal, M. (2021). State of art design aspects of wearable, mobile, and flexible antennas for modern communication wireless systems. International Journal of Communication Systems, 34(15), e4934.

[7]. He, J., & Wei, X. (2016, August). A compact dualband antenna for C-band applications. In 2016 17th International Conference on Electronic Packaging Technology (ICEPT) (pp. 1445-1446). IEEE.

[8]. Kaya, A. (2007). High isolation 2.4/2.6 GHz dual band full duplex patch antenna transceiver for WLAN. Microwave and Optical Technology Letters, 49(11), 2843-2848.

[9]. Lee, Y. C., & Sun, J. S. (2008). A new printed antenna for multiband wireless applications. IEEE Antennas and Wireless Propagation Letters, 8, 402-405.

[10]. Li, Y., Li, W., & Ye, Q. (2013). A compact asymmetric coplanar strip fed dual band antenna for 2.4/5.8 GHz WLAN applications. Microwave and Optical Technology Letters, 55(9), 2066-2070.

[11]. Nazari, M. E., Huang, W., & Alavizadeh, Z. (2020). Return loss-bandwidth evaluation for electrically small microstrip antennas. Journal of Electromagnetic Waves and Applications, 34(16), 2220-2235.

[12]. Rai, B. S. (2014, April). Bandwidth enhancement of Wang shape microstrip patch antenna for wireless system. In 2014 Fourth International Conference on Communication Systems and Network Technologies (pp. 11-15). IEEE.

[13]. Ritosa, P., Korosec, T., Tratnik, J., Naglic, L., & Batagelj, B. (2009, May). Adaptive WiMAX subscriber antenna for 2.6 GHz and 3.45 GHz. In IEEE EUROCON 2009 (pp. 46-51). IEEE.

[14]. Shuai, C. Y., & Wang, G. M. (2018). Substrate integrated low profile unidirectional antenna. IET Microwaves, Antennas & Propagation, 12(2), 185-189.

[15]. Xu, Q., Huang, Y., Xing, L., Song, C., Tian, Z., Alja'afreh, S. S., & Stanley, M. (2016). 3-D antenna radiation pattern reconstruction in a reverberation chamber using spherical wave decomposition. IEEE Transactions on Antennas and Propagation, 65(4), 1728-1739.

[16]. Yang, X., Kong, F., Liu, X., & Song, C. (2014). A CPWfed triple-band antenna for WLAN and WiMAX applications. Radioengineering, 23(4), 1086-1091.

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Research Paper

Design of Duty Cycle Correction Circuit using ASIC Implementation for High Speed Communication

Siddesh K. B.* , Roopa S., Farzana Parveen B. A.*, Tanuja T.****

*-**** Department of Electronics and Communication Engineering, Sri Jagadguru Murugarajendra Institute of Technology, Chitradurga, Visvesvaraya Technological University, Karnataka, India.

Siddesh, K. B., Roopa, S., Parveen, B. A. F., and Tanuja T. (2023). Design of Duty Cycle Correction Circuit using ASIC Implementation for High Speed Communication. i-manager’s Journal on Electronics Engineering, 13(3), 33-39. https://doi.org/10.26634/jele.13.3.19969

Abstract

This research proposed an accurate Duty Cycle Correction (DCC) circuit for high-frequency systems with high measurement accuracy. It is a crucial component of Very Large Scale Integration (VLSI) circuits and is applied as a percentage of the measured average power of a modulated signal to obtain the signal power. This circuit uses two stages of correction, with the first stage performing course correction and the second stage performing fine corrections. This allows the power to be determined during the pulse given the measurement of the average power of a modulated signal with a known duty cycle. DCC have improved stability, correction range, and operating frequency compared with mixed-signal and all-digital DCCs. In this analysis, the duty cycle correction circuits and their significance in Application Specific Integrated Circuit (ASIC) design, along with typical implementation methods, are discussed.

References

[1]. Beauquier, C., Duperray, D., Jabbour, C., Desgreys, P., Frappé, A., & Kaiser, A. (2021, November). Analog Duty Cycle Controller Using Backgate Body Biasing For 5G Millimeter Wave Applications. In 2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) (pp.1-4). IEEE.

[2]. Chu, W., Chen, W. H., & Huang, S. Y. (2020, October). Duty-Cycle Correction for a Super-Wide Frequency Range from 10MHz to 1.2 GHz. In 2020 IEEE 38th International Conference on Computer Design (ICCD) (pp. 457-460). IEEE.

[3]. Kaysici, H. I., & Ergün, S. (2021, May). Duty Cycle Correction Circuit and Its Application for High Speed Random Number Generation. In 2021 IEEE International Symposium on Circuits and Systems (ISCAS) (pp. 1-5). IEEE.

[4]. Lin, C. Y., & Hsu, H. S. (2019, May). Design of A 0.8 GHz-3GHz Duty-Cycle Corrector with a 20%-80% Input Duty Cycle. In 2019 IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW) (pp. 1-2). IEEE.

[5]. Mekky, R. H., Fortin, G., Venditti, M., & Leclerc, S. (2020, October). A Multi-Range Duty Cycle Correction Circuit for Multi-Standard Transceivers in 7 nm FinFET. In 2020 IEEE International Symposium on Circuits and Systems (ISCAS) (pp. 1-5). IEEE.

[6]. Ngieng, B. S. Y., Ahmad, N., Uttraphan, C., & Jubadi, W. M. (2021, December). Development of Compact Automated Home System Controller using ASIC Design Flow. In 2021 6th IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE) (Vol. 6, pp. 1-6). IEEE.

[7]. Nimmagadda, S. C., & Dubey, H. B. (2023, January). Programmable Delay Line with inherent duty cycle correction. In 2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID) (pp. 81-86). IEEE.

[8]. Vazgen, M. S., Arman, A. A., Manvel, G. T., Hakob, K. T., Karo, S. H., & Ruben, M. H. (2019, April). Duty-cycle correction circuit for high speed interfaces. In 2019 IEEE 39th International Conference on Electronics and Nanotechnology (ELNANO) (pp. 42-45). IEEE.

[9]. Yoon, H., Jung, W., Park, J., Byun, J., Jin, H., Cho, H., ... & Lee, S. H. (2021, September). A 3.2-12.8 Gb/s DutyCycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics. In ESSCIRC 2021-IEEE 47th European Solid State Circuits Conference (ESSCIRC) (pp. 463-466).IEEE.

[10]. Zhang, J., & Meng, X. (2020, November). A 0.5-5 GHz 0.3-mW 50% duty-cycle corrector in 65-nm CMOS. In 2020 IEEE Region 10 Conference (TENCON) (pp. 351-354). IEEE.

[11]. Zhang, J., & Meng, X. (2020, November). A 0.5-5 GHz 0.3-mW 50% duty-cycle corrector in 65-nm CMOS. In 2020 IEEE Region 10 Conference (TENCON) (pp. 351-354). IEEE.

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Review Paper

A Review on Flexible and Foldable Displays

M. Theodore Kingslin*

Department of Electronics and Communication Engineering, R.M.K. College of Engineering & Technology, Thiruvallur, Tamil Nadu, India.

Kingslin, M. T. (2023). A Review on Flexible and Foldable Displays. i-manager’s Journal on Electronics Engineering, 13(3), 40-46. https://doi.org/10.26634/jele.13.3.20029

Abstract

Flexible and foldable displays are new types of displays that can bend, twist, and fold without breaking. The screens used for making foldable devices are known as Organic Light Emitting Diode (OLED), which are made up of organic compounds; when electricity is passed through them, they emit their own light. Flexible displays require highly dependable flexible OLEDs; however, there are still problems with flexible encapsulation technology that need to be addressed. This study examines innovations in the field of flexible and foldable displays and explores fundamental technologies, applications, advantages, and challenges. The working principles, structure, advantages, and applications of flexible and foldable display technologies are also discussed. This review examines the ongoing research and development efforts aimed at addressing these hurdles and provides insights into the future of flexible display technologies.

References

[1]. Cairns, D. R., Broer, J. D., & Crawford, G. P. (2023). Flexible Flat Panel Displays. John Wiley & Sons, (pp. 287-300).

[2]. Díez-Pascual, A. M., & Rahdar, A. (2022). Graphenebased polymer composites for flexible electronic applications. Micromachines, 13(7), 1123.

[3]. Flexible Display. (n.d.). In Wikipedia.

[4]. Huitema, E. (2012). The future of displays is foldable. Information Display, 28(2-3), 6-10.

[5]. Jin, M., Zhou, G., & Shui, L. (2016). Advanced materials for reflective display applications. Design, Fabrication, Properties and Applications of Smart and Advanced Materials, (pp. 468-496).

[6]. Koden, M. (2022). Flexible OLEDs: Fundamental and Novel Practical Technologies. Springer Nature.

[7]. Wang, R., Xiang, H., Tu, S., Li, Y., Zhou, Y., & Zeng, H. (2022). Full solution-processed heavy-metal-free miniQLEDs for flexible display applications. Nanoscale, 14(35), 12736-12743.

[8]. Zhang, D., Huang, T., & Duan, L. (2020). Emerging self emissive technologies for flexible displays. Advanced Materials, 32(15), 1902391.

[9]. Zhao, Z., Liu, K., Liu, Y., Guo, Y., & Liu, Y. (2022). Intrinsically flexible displays: Key materials and devices. National Science Review, 9(6), 1-18.

[10]. Moro, L., & Visser, R. J. (2023). Encapsulation of Flexible Displays: Background, Status, and Perspective. Flexible Flat Panel Displays, 229-254.

i-manager's Journal on Electronics Engineering (JELE)

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Volume 13 Issue 3 April - June 2023

Design and Analysis of Ternary Delay Flip-Flop Implemented with Carbon Nanotube Field Effect Transistor

Pradeep Singh Yadav* , Chinmay Chandrakar**, Anil Kumar Sahu***

* Department of Electronics and Communication, Sagar Institute of Science and Technology, Bhopal, Madhya Pradesh, India. ** Shri Shankaracharya Technical Campus, Bhilai, India. *** Bharat Institute of Engineering and Technology, Hyderabad, India.

Yadav, P. S., Chandrakar, C., and Sahu, A. K. (2023). Design and Analysis of Ternary Delay Flip-Flop Implemented with Carbon Nanotube Field Effect Transistor. i-manager’s Journal on Electronics Engineering, 13(3), 1-10. https://doi.org/10.26634/jele.13.3.19808

Abstract

References

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The Design of a Low-Power 4-Bit Barrel Shifter for a Current Steering DAC using Optimized Multiplexers in 65 nm Technology

Ashok Kumar Adepu* , Balaji Narayanam**

*-** Department of Electronics and Communication Engineering, Jawaharlal Nehru Technological University, Kakinada, Andhra Pradesh, India.

Adepu, A. K., and Narayanam, B. (2023). The Design of a Low-Power 4-Bit Barrel Shifter for a Current Steering DAC using Optimized Multiplexers in 65 nm Technology. i-manager’s Journal on Electronics Engineering, 13(3), 11-22. https://doi.org/10.26634/jele.13.3.19829

Abstract

References

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A Miniaturized Antenna for Mobile Broad-Band/Cordless Phones/Wireless Audio Devices/ISM

Prakshep Kumar Rai* , Shambhavi M. Shukla**, Chandan***, Ashutosh K. Singh****

*-**** Department of Electronics and Communication Engineering, Dr. Ram Manohar Lohia Avadh University, Ayodhya, Uttar Pradesh, India.

Rai, P. K., Shukla, S. M., Chandan, and Singh, A. K. (2023). A Miniaturized Antenna for Mobile Broad-Band/Cordless Phones/Wireless Audio Devices/ISM. i-manager’s Journal on Electronics Engineering, 13(3), 23-32. https://doi.org/10.26634/jele.13.3.19832

Abstract

References

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Design of Duty Cycle Correction Circuit using ASIC Implementation for High Speed Communication

Siddesh K. B.* , Roopa S.**, Farzana Parveen B. A.***, Tanuja T.****

*-**** Department of Electronics and Communication Engineering, Sri Jagadguru Murugarajendra Institute of Technology, Chitradurga, Visvesvaraya Technological University, Karnataka, India.

Siddesh, K. B., Roopa, S., Parveen, B. A. F., and Tanuja T. (2023). Design of Duty Cycle Correction Circuit using ASIC Implementation for High Speed Communication. i-manager’s Journal on Electronics Engineering, 13(3), 33-39. https://doi.org/10.26634/jele.13.3.19969

Abstract

References

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A Review on Flexible and Foldable Displays

M. Theodore Kingslin*

Department of Electronics and Communication Engineering, R.M.K. College of Engineering & Technology, Thiruvallur, Tamil Nadu, India.

Kingslin, M. T. (2023). A Review on Flexible and Foldable Displays. i-manager’s Journal on Electronics Engineering, 13(3), 40-46. https://doi.org/10.26634/jele.13.3.20029

Abstract

References

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Pradeep Singh Yadav* , Chinmay Chandrakar, Anil Kumar Sahu*

* Department of Electronics and Communication, Sagar Institute of Science and Technology, Bhopal, Madhya Pradesh, India.

Shri Shankaracharya Technical Campus, Bhilai, India.

* Bharat Institute of Engineering and Technology, Hyderabad, India.

Prakshep Kumar Rai* , Shambhavi M. Shukla, Chandan*, Ashutosh K. Singh****

Siddesh K. B.* , Roopa S., Farzana Parveen B. A.*, Tanuja T.****