An analytical approach to Network with IoT security using NodeMCU access point- Prevention Technique
AUDIO CRYPTOGRAPHY USING AES ALGORITHM TECHNIQUE
ULTRA WIDEBAND TECHNOLOGY
Smart Rover-Voice Control Bluetooth Control Robot to Avoid Obstacles
A Review of Quality Assurance Texture for Highly Pigmented Iris Recognition Using an Optimal Wavelength Band
FEATURE EXTRACTION AND CLASSIFICATION OF DIFFERENT HAND MOVEMENTS FROM THE EMG SIGNAL USING LINEAR DISCRIMINANT ANALYSIS CLASSIFIER
The Impact of Substrate Doping Concentration on Electrical Characteristics of 45nm Nmos Device
A Study on Globally Asynchronous and locally Synchronous System
Performance Analysis of Modified Source Junctionless Fully Depleted Silicon-on-Insulator MOSFET
Method of 2.5 V RGMII Interface I/O Duty Cycle and Delay Skew Enhancement
Automatic Accident Detection and Tracking of Vehicles by Using MEMS
Efficient Image Compression Algorithms Using Evolved Wavelets
Computer Modeling and Simulation of Ultrasonic Signal Processing and Measurements
Effect of Nano-Coatings on Waste-to-Energy (WTE) plant : A Review
ANFIS Controlled Solar Pumping System
FEATURE EXTRACTION AND CLASSIFICATION OF DIFFERENT HAND MOVEMENTS FROM THE EMG SIGNAL USING LINEAR DISCRIMINANT ANALYSIS CLASSIFIER
Flip-flops serve as fundamental memory storage elements in digital circuits, and their efficiency significantly affects overall circuit performance. The aim of this study is to create a D flip-flop based on ternary logic and evaluate its performance in comparison to flip-flops that have already been designed. The proposed D flip-flop design leverages Carbon Nanotube Field Effect Transistors (CNTFETs). CNTFETs offer unique properties that can enhance the speed and power efficiency of flip-flop design. To evaluate the performance of the proposed design, it was simulated using the HSPICE simulator with a 32 nm Stanford CNTFET model. The simulation parameters include a power supply voltage of 0.9 volts and an operating frequency of 1 GHz. These specific settings allow researchers to analyze the behavior and performance of flip-flops under realistic operating conditions. By comparing the simulation results of the proposed D flipflop with the performance of previously designed flip-flops, the improvements are assessed in terms of the speed and power consumption. The simulation results provide valuable insights into the efficiency, reliability, and responsiveness of the proposed design. The findings of this research contribute to the advancement of digital circuit design by introducing a novel D flip-flop based on ternary logic and CNTFET technology. The goal is to enhance the overall performance efficiency of digital circuits, particularly in applications where D flip-flops are used as building blocks such as shift registers.
CMOS technology scaling has paved the way for a faster and more complex integration. Low-power techniques have become crucial because of the demand for low power consumption and high speed. The main objective of this research is to utilize low-power techniques to implement a 4-bit barrel shifter that can shift or rotate data using any number of bits within a single cycle. Gate Diffusion Input (GDI), modified GDI, and full-swing GDI logic have been employed to implement a 2:1 multiplexer, among which the modified GDI-based multiplexer stands out because of its minimal power consumption. Consequently, a 4-bit barrel shifter is implemented using a modified GDI-based multiplier. All designs and simulations were performed using the Cadence Virtuoso tool in UMC 65 nm technology. This technology enables the accurate analysis and assessment of the designed barrel shifter, considering the characteristics and limitations of the 65 nm process. This study focused on leveraging low-power techniques to implement a 4-bit barrel shifter to address the industry's demand for power-efficient solutions. The modified GDI-based multiplexer is a promising choice that provides a balance between low power consumption and high performance. The use of advanced design tools and selected technology further ensures accurate simulations and evaluations of the proposed design.
This research introduces the design and simulation of a monopole antenna with a simple ground plane, specifically developed for dual-band communication. The antenna consists of a radiating patch, feed line, and ground plane, and it was fabricated on an FR-4 substrate. The operating frequency bands of the antenna cover 2.5–2.7 GHz and 3.9–4.6 GHz. By carefully selecting the dimensions, the antenna achieves resonance frequencies at 2.6 GHz and 4.2 GHz, with corresponding bandwidths of 200 MHz and 700 MHz. The research provided excellent impedance matching for the antenna, as indicated by the measured return loss (S11) values of -29.35 dB and -22.48 dB, surpassing the required criterion of S11 < -10 dB. The compact size of the antenna, measuring 12×24×1.6 mm³, makes it highly suitable for applications with space limitations. The antenna performance was extensively analyzed through simulations utilizing High-Frequency Structure Simulator (HFSS) software. The results validate its effectiveness for two specific frequency bands:2.6 GHz for mobile broadband service and 4.2 GHz for various applications such as cordless phones, wireless audio devices, and industrial, Scientific, and Medical Networks (ISM). This research lays a solid foundation for future developments in dual-band communication antennas, offering potential benefits in terms of connectivity and communication efficiency.
This research proposed an accurate Duty Cycle Correction (DCC) circuit for high-frequency systems with high measurement accuracy. It is a crucial component of Very Large Scale Integration (VLSI) circuits and is applied as a percentage of the measured average power of a modulated signal to obtain the signal power. This circuit uses two stages of correction, with the first stage performing course correction and the second stage performing fine corrections. This allows the power to be determined during the pulse given the measurement of the average power of a modulated signal with a known duty cycle. DCC have improved stability, correction range, and operating frequency compared with mixed-signal and all-digital DCCs. In this analysis, the duty cycle correction circuits and their significance in Application Specific Integrated Circuit (ASIC) design, along with typical implementation methods, are discussed.
Flexible and foldable displays are new types of displays that can bend, twist, and fold without breaking. The screens used for making foldable devices are known as Organic Light Emitting Diode (OLED), which are made up of organic compounds; when electricity is passed through them, they emit their own light. Flexible displays require highly dependable flexible OLEDs; however, there are still problems with flexible encapsulation technology that need to be addressed. This study examines innovations in the field of flexible and foldable displays and explores fundamental technologies, applications, advantages, and challenges. The working principles, structure, advantages, and applications of flexible and foldable display technologies are also discussed. This review examines the ongoing research and development efforts aimed at addressing these hurdles and provides insights into the future of flexible display technologies.
