Loss Distribution Methodology with a Sense Of Emission Dispatch
Low Power Optimization Technique Based Linear Feedback Shift Register
Leakage Power Reduction Using Multi Modal Driven Hierarchical Power Mode Switches
Validation of IOV chain using OVM Technique
Performance of Continuous and Discontinuous Space Vector Pwm Technique for Open End Winding Induction Motor Drive
Electronic Circuit Design for Electromagnetic Compliance through Problem-Based Learning
Trioinformatics: The Innovative and Novel Logic Notation That Defines, Explains, and Expresses the Rational Application of The Law of Trichotomy for Digital Instrumentation and Circuit Design
Design Of a Novel Gated 5T SRAM Cell with Low Power Dissipation in Active and Sleep Mode
A Two Stage Power Optimized Implantable Neural Amplifier Based on Cascoded Structures
An Efficient Hybrid PFSCL based Implementation of Asynchronous Pipeline
This paper discusses the trends in ESD protection design used in I/O libraries in advanced CMOS and FinFet technologies. The trends and guidelines are provided predominantly for low voltage I/O libraries that are commonly used for general purpose interfaces and industrial low voltage interfaces such as, GPIO, DDR, LVDS, etc. Additionally, the impact of technology scaling on ESD qualification targets for CDM stress is considered.
In digital VLSI design calculation of setup/hold time is very important part. Setup/hold time defines the maximum speed of the circuit on which it can work. When a design is completed the first step is to check the timing performances of circuit using Static Timing Analysis (STA) (Scheffer et al., 2006). Accuracy of STA depends on the data described in standard cell libraries. So accuracy of STA depends on accuracy of standard cell library characterization (Cirit, 1991; Roethig, 2003; Patel, 1990; Phelps, 1991). As the technology is scaling down, the characterization of standard cell libraries are becoming more time consuming and requires large computational time. Further due to process, voltage and temperature (PVT) variations standard cell library characterization is done for various PVT, this increase characterization greatly. In this paper we present a novel approach to speed up standard cell library characterization for true single phase clocked (TSPC) latch (Yuan and Svensson, 1989) setup time by developing a linear setup time model. In this model setup time varies linearly with output load capacitance (CL) and input transition time (TR). We express setup time model coefficients as a function of logic gate size (Wn) of the latch. We do not use device current/capacitance models in derivation of model, so it is valid with technology scaling. Using proposed model approximately 70% SPICE simulation during the standard cell library characterization for latch setup time can be saved. We observed that setup time calculated using proposed model is within 2% (average) of that calculated using simulation.
The complexity of circuit designing has been increasing by immense increase of applications in this field. One of the major complexities is power dissipation. Reversible Logic Design can be used to reduce this complexity, which is gaining demand day by day and having applications in low power CMOS circuits, optical computing, quantum computing, and nanotechnology. Power dissipation of VLSI chips becomes a crucial aspect as complexity of applications grow very rapidly. High power dissipation in electronic devices decreases battery lifetime. A router is a key component for transmitting data between two users. It is a networking device, commonly specialized for forwarding data packets between computer networks. In this paper, the author has designed a router using reversible logic in QCA designer. An advantage of quantum phenomena is taken by QCA and, it may ultimately slow down the progress in scaling down CMOS circuits.
The space environment is characterized with various energetic particles like cosmic rays, cosmic neutrons, alpha particles and heavy ions from solar flares. Nowadays most of the circuits used in space applications are being made of Complementary Metal Oxide Semiconductor (CMOS). The technology is scaling down, i.e. reduction in supply voltage and node capacitances lead to decrease of amount of charge stored on a node, which makes the circuit more vulnerable towards particle induced charge. When amount of this particle induced charge is high enough, a transient fault appears like a glitch called as Single Event Transient (SET). As the feature size scales down, the vulnerability of circuits to radiation induced error has also been increased, as this may cause Double Node Upset (DNU) i.e Single Event Double Node Upset (SEDU). In this paper, some of the best known designs to mitigate the Single Event Upset as well as Single Event Double Node Upset in 65 nm CMOS technology using standard TSPICE tool has been discussed. The comparison of those designs on the same platform i.e 65 nm technology is presented, their power consumption and propagation delay are also compared.
Today, the utilization of pre-silicon system verification strategies within the business cannot guarantee that every error in system computer code or system hardware are discovered and removed before silicon (Si) becomes offered. Some system errors solely show up once the application software package is executed on the particular Si. Presently, the business spends on average more than 50% of the overall project time on post-silicon validation and debugging. At this stage, it is still terribly tough and time intense to rectify issues that ends up in higher development price, slippery deadlines, and a possible loss of consumer. Therefore, an efficient method for debugging errors is used called Design for Debug (DFD). The DFD strategies prevailing nowadays are everywhere for over a decade. There are numerous examples throughout the industry, where the inclusion and subsequent use of DFD features have contributed significantly to a reduction in Time to Market (TTM). This paper proposes a DFD Validation of In-die variation (IDV), On-die Droop inducer (ODI), and Voltage Droop monitor (VDM) to reduce manufacturing defects or errors of chip, such as Variation of Process, Power Domain voltages and also variation of current inducer needed for chip.
Research on reversible logic gates has become one of the interesting fields in the world of electronics. This has been proved to be one of the most reliable logics that originates its place in low power CMOS skills, Nano and optical calculation and many more. These broadsheet offers the comparison of different reversible logic gates in expressions of quantum cost, delay, transistor charge, and also implementation of one of the alterable logic gates, i.e. Peres gate in a conventional half adder with the help of an efficient algorithm. The work is performed in Xilinx using Verilog coding. The simulation result shows improved efficiency, low power, and low area consumption as related to the standard half adder. This half adder can be utilized in different applications, where circuit comprising of a conventional half adder can be replaced by Peres Half Adder (HAP).
