References
[1]. Chen, S. H., Hellings, G., Thijs, S., Linten, D., & Groeseneken, G. (2016). Process options impact on esd diode performance in bulk FinFET technology. IEEE Transactions on Electron Devices, 63(9), 3424-3431.
[2]. Duvvury, C., Ashton, R., Semiconductor, O. N., Righter, A., & Devices, A. (2012). Discontinuing use of the machine model for device ESD qualification. Compliance Magazine, 56-63.
[3]. EOS/ESD Association, Inc. Industry Council White Paper 2: A Case for Lowering Component Level CDM ESD Specifications and Requirements. Retrieved from https://www.esda.org/standards/complimentary-downloads/ view/1871
[4]. Huang, J. B., & Wang, G. (2001, October). ESD protection design for advanced CMOS. In Advances in Microelectronic Device Technology (Vol. 4600, pp. 123- 132). International Society for Optics and Photonics.
[5]. Industry Council on ESD Target Levels. (April, 2010). White Paper “A Case for Lowering Component Level CDM ESD Specification and Requirements,” Rev 2.0. Retrieved from http://www.esdindustrycouncil.org/ic/docs/Industry%20Council%20White%20Paper%202%20Rev2%20Apr%202010.pdf
[6]. Kuo-Hsuan Meng, et al. (2017). ESD design and physical architecture of the 16FFC IO libraries, NXP Semiconductors, Austin.
[7]. Lee, J. H., Prabhu, M., Korablev, K., Singh, J., Natarajan, M. I., & Pandey, S. M. (2015, April). Methodology to achieve planar technology-like ESD performance in FINFET process. In Reliability Physics Symposium (IRPS), 2015 IEEE International (pp. 1-3F.3.6). IEEE.
[8]. Li, J., Gauthier, R., Li, Y., & Mishra, R. (2014, September). ESD device performance analysis in a 14 nm FinFET SOI CMOS technology: Fin-based versus planarbased. In Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2014 36th (pp. 1-6). IEEE.
[9]. Okano, K., Izumida, T., Kawasaki, H., Kaneko, A., Yagishita, A., Kanemura, T., ... & Ono, T. (2005, December). Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length. In Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International (pp. 721-724). IEEE.
[10]. Qualcomm Technologies, Inc. (2018). Qualcomm® Snapdragon™ 820E Processor (APQ8096SGE), Device Specification (p. 116). Retrieved on February 9, 2018 from https://developer.qualcomm. com/download/sd820e/qualcomm-snapdragon- 820eprocessor-apq8096sge-device-specification.pdf
[11]. Semenov, O., & Somov, S. (2008). ESD protection design for I/O libraries in advanced CMOS technologies. Solid-State Electronics, 52(8), 1127-1139.
[12]. Singh, J., Jerome, C., Wei, A., Miller, R., Arnaud, B., Lili, C., ... & Kumar, A. (2014, June). Analog, RF, and ESD device challenges and solutions for 14 nm FinFET technology and beyond. In VLSI Technology (VLSITechnology): Digest of Technical Papers, 2014 Symposium on (pp. 1-2). IEEE.
[13]. Stockinger, M., Miller, J. W., Khazhinsky, M. G., Torres, C. A., Weldon, J. C., Preble, B. D., ... & Kamat, V. G. (2005). Advanced rail clamp networks for ESD protection. Microelectronics Reliability, 45(2), 211-222.
[14]. Wong, R., Fung, R., & Wen, S. J. (2013, October). Networking industry trends in ESD protection for high speed IOs. In ASIC (ASICON), 2013 IEEE 10th International Conference on (pp. 1-4). IEEE.
