Loss Distribution Methodology with a Sense Of Emission Dispatch
Low Power Optimization Technique Based Linear Feedback Shift Register
Leakage Power Reduction Using Multi Modal Driven Hierarchical Power Mode Switches
Validation of IOV chain using OVM Technique
Performance of Continuous and Discontinuous Space Vector Pwm Technique for Open End Winding Induction Motor Drive
Electronic Circuit Design for Electromagnetic Compliance through Problem-Based Learning
Trioinformatics: The Innovative and Novel Logic Notation That Defines, Explains, and Expresses the Rational Application of The Law of Trichotomy for Digital Instrumentation and Circuit Design
Design Of a Novel Gated 5T SRAM Cell with Low Power Dissipation in Active and Sleep Mode
A Two Stage Power Optimized Implantable Neural Amplifier Based on Cascoded Structures
An Efficient Hybrid PFSCL based Implementation of Asynchronous Pipeline
This article presents a scalable power-gating scheme approach to reduce leakage power using intermediate poweroff modes. An important limitation in power-gating scheme is its variations with wakeup time during activation mode changes, as is often the case. The authors have proposed a novel power-gating scheme that are accomplished by hierarchical mode activation to reduce worst case delay bound. The system combines the advantages of leakage power reduction and wake up time optimization. The influence of power-gating scheme on circuit performance is studied and concluded that finite power-off modes, scalable modes are important for good performance. Key selection of power-off modes over entire circuit is complex and it is computationally more expensive. To get more accurate modes with finite trade off in wake up time, this new approach gives near-perfect ways of isolating modes from other changes. The complete power-gating scheme system was evaluated on a multiplier logic core as a test sample and also compared against well known power-gating schemes.
In today's smart digital world, for any digital circuit, one of the most vital parts is Static Random Access Memory (SRAM). The power consumption, speed, area etc. have been the major areas of concern in the evolution of different memory architectures. Researchers are working on the modification of basic 6T SRAM cell to meet their requirements by optimizing the performance parameters of SRAM. In the present research work, a novel 7T SRAM cell has been designed, having both low latency and low power. The proposed design has allowed control over threshold voltage and reduced the leakage current. As a consequence, there is a reduction in the static power consumption and load capacitance of SRAM. Dynamic power consumption, Static power consumption, Unit cell delay, Power Delay Product (PDP), Static Noise Margin (SNM) and Write SNM are estimated for 6T and 7T for comparison. On comparison of the performance parameters, the proposed 7T SRAM cell was found to be the cell with least power consumption along with lowest latency among the two cells. Most of the compared parameters show an improvement in the performance of the proposed design as compared to the regular 6T configuration of SRAM. This research was carried out using Cadence Virtuoso Tools on 90 nm technology with Assura Verification tool and Spectre simulation tool.
In this paper, a decoupled Space Vector Pulse Width Modulation (SVPWM) technique for indirect vector controlled induction motor drive in open end winding configuration is presented. The decoupled space vector PWM technique provides independent control of each inverter in an Open End Winding Induction Motor (OEWIM) drive. With this advantage, failure of any one inverter in the drive can be operated with reduced output voltage. With the freedom in selecting different voltage vectors for each inverter, this decoupled PWM technique also reduces the Common Mode Voltage (CMV), when compared with other coupled PWM techniques. Within a sample time T , in conventional s continuous decoupled space vector PWM technique, each inverter is operated with zero voltage vectors and active voltage vectors. In this paper to reduce the CMV with good quality of output voltage inverters with different continuous and discontinuous PWM (DPWM) techniques were presented. Within a sample time T , these PWM techniques use active s vectors, but zero voltage vectors may be replaced by new active vectors or zero vectors which are unequally shared. The performance of these PWM techniques were analyzed in MatLab/Simulink and the results were presented.
Reversible Logic is the dominating field of research in low power Very-Large-Scale Integration (VLSI). In recent time, reversible logic has gained special attention in order to reduce power consumption mainly in concern to digital logic design. The main aim of this paper is to realize and synthesize shift counters like Ring counter and Johnson ring counter using reversible logic. Shift Counter is a sequential circuit that performs counting through shifting operation in a loop fashion. The output of last register of the circuit will be fed to the input of first register. Ring counter owns its applications in clock division circuits, square wave generators, hardware logic design of Application-Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA) circuits etc., Ring counter and Johnson Ring counter are designed using reversible logic to reduce power dissipation. A Boolean function f (i1 , i2 , i3 , ……, i n) having 'n' inputs and 'm' outputs is said to be logically reversible, if the number of inputs are equal to the number of outputs ( i.e. n = m) and the input pattern maps uniquely to the output pattern. Few reversible logic gates present in the literature are NOT gate, Feynman Gate (CNOT gate), Double Feynman Gate, Peres Gate, TR gate, Seynman Gate etc. The reversible gate must run both in forward and backward directions such that the inputs can be retrieved with the knowledge of outputs. The two limitations of logical reversibility are Fan-out and Feed-back are not allowed. Signals from required output lines are duplicated to desired lines using additional reversible combinational circuits to overcome the Fan-out limitation. Reversible Logic has applications in various fields like Quantum Computing, Optical Computing, Nanotechnology, Computer Graphics, Low power VLSI etc. Reversible logic has gained essence in recent years largely due to its property of low power consumption and low heat dissipation. In this paper, shift registers like shift right register and shift left register which have less heat dissipation and low power consumption is proposed. Till date, shift counters are not yet designed using reversible logic. In this paper, an attempt has been made to design shift counters like ring counter and Johnson ring counter using reversible logic. The designed circuits are analysed in terms of Quantum Cost (QC), Garbage Outputs (GO) and number of gates. The circuit has been designed and simulated using Xilinx software.
To design the computing system, energy efficiency is an important issue to be considered. Approximate computing has been evolved as an optimistic solution for energy efficient design of digital systems. While designing these systems, power dissipation is the significant issue for integrated circuits in nanometric Complementary Metal Oxide Semiconductor (CMOS) technology. Approximate implementations of a circuit have been considered as a potential solution for applications in which exact result is not required, which eventually reduces power consumption. The approximate computing has various research activities which varies from programming languages to transistor levels. Here, different approximate adder circuits have been reviewed, which are based on XOR and XNOR gates, and majority gates. Where emerging nanotechnology exploit these majority gates, combining with approximate computing gives the potential to reduce power consumption. Approximate circuit provides low power consumption, low transistor count, less area and reduced delay. Hence it is a good option, when strict exact solution is not required. This paper is about the survey on arithmetic circuits and different design topologies such as Quantum Dot Cellular Automata (QCA)and Nanomagnetic Logic (NML)
The Space environment is characterized with various energetic particles like cosmic rays, cosmic neutrons, alpha particles,heavy ions from solar flares. Nowadays most of circuit used in space applications being made using CMOS. As the technology scaling down i.e reduction in supply voltage and node capacitances leads in decrease of amount of charge stored on a node,which makes the circuit more vulnerable towards particle induced charge, when amount of this particle induced charge is high enough,a transient fault gets appear like a glitch called as Single Event Transient(SET). As the feature size scales down, the vulnerability of circuits to radiation induced error has also been increased, as this may cause Double node upset i.e Single Event Double NodeUpset(SEDU).Here we would design and discuss some of the best known designs to mitigate the Single Event Upset as well as SingleEvent Double Node Upset in 65nm CMOS technology using standard TSPICE tool.We are comparing those designs on the same platform i.e 65nm technology and compare their power consumption and propagation delay.
