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Radiation Immune Latch design in CMOS Technology:A Review

Sandhya Kesharwani*, Vaibhav Dedhe**

* PG Scholar, Department of Electronics and Telecommunication Engineering, Shri Shankaracharya Technical Campus, Chhattisgarh, India.

** Assistant Professor, Department of Electronics and Telecommunication Engineering, Shri Shankaracharya Technical Campus, Chhattisgarh, India

Periodicity:March - May'2018
DOI : https://doi.org/10.26634/jcir.6.2.14290

Abstract

The Space environment is characterized with various energetic particles like cosmic rays, cosmic neutrons, alpha particles,heavy ions from solar flares. Nowadays most of circuit used in space applications being made using CMOS. As the technology scaling down i.e reduction in supply voltage and node capacitances leads in decrease of amount of charge stored on a node,which makes the circuit more vulnerable towards particle induced charge, when amount of this particle induced charge is high enough,a transient fault gets appear like a glitch called as Single Event Transient(SET). As the feature size scales down, the vulnerability of circuits to radiation induced error has also been increased, as this may cause Double node upset i.e Single Event Double NodeUpset(SEDU).Here we would design and discuss some of the best known designs to mitigate the Single Event Upset as well as SingleEvent Double Node Upset in 65nm CMOS technology using standard TSPICE tool.We are comparing those designs on the same platform i.e 65nm technology and compare their power consumption and propagation delay.

Keywords

Single Event Upset,Single event transient,Single Event double upset,C element,Radiation Hardened latch

How to Cite this Article?

Kesharwani, S., and Dedhe, V. (2018). Radiation Immune Latch Design In CMOS Technology: A Review. i-manager’s Journal on Circuits and Systems, 6(2), 39-46. https://doi.org/10.26634/jcir.6.2.14290

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