A Review on Approximation Techniques for Arithmetic Adders

S. M. Bhagat*
Department of Electronics and Telecommunication Engineering, Pimpri Chinchwad College of Engineering, Pune, India.
Periodicity:March - May'2018
DOI : https://doi.org/10.26634/jcir.6.2.14313

Abstract

To design the computing system, energy efficiency is an important issue to be considered. Approximate computing has been evolved as an optimistic solution for energy efficient design of digital systems. While designing these systems, power dissipation is the significant issue for integrated circuits in nanometric Complementary Metal Oxide Semiconductor (CMOS) technology. Approximate implementations of a circuit have been considered as a potential solution for applications in which exact result is not required, which eventually reduces power consumption. The approximate computing has various research activities which varies from programming languages to transistor levels. Here, different approximate adder circuits have been reviewed, which are based on XOR and XNOR gates, and majority gates. Where emerging nanotechnology exploit these majority gates, combining with approximate computing gives the potential to reduce power consumption. Approximate circuit provides low power consumption, low transistor count, less area and reduced delay. Hence it is a good option, when strict exact solution is not required. This paper is about the survey on arithmetic circuits and different design topologies such as Quantum Dot Cellular Automata (QCA)and Nanomagnetic Logic (NML)

Keywords

Nanometric Complementary Metal Oxide Semiconductor (CMOS), Approximate Computing, XOR/XNOR, Quantum Dot Cellular Automata (QCA), Nanomagnetic Logic ( NML).

How to Cite this Article?

Bhagat, S. M. (2018). A Review on Approximation Techniques for Arithmetic Adders. i-manager’s Journal on Circuits and Systems, 6(2), 33-38. https://doi.org/10.26634/jcir.6.2.14313

References

[1]. Akbari, O., Kamal, M., Afzali-Kusha, A., & Pedram, M. (2016). RAP-CLA: A reconfigurable approximate carry look-ahead adder. IEEE Transactions on Circuits and Systems II: Express Briefs.
[2]. Gupta, V., Mohapatra, D., Raghunathan, A., & Roy, K. (2013). Low-power digital signal processing using approximate adders. IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, 32(1), 124-137.
[3]. Han, J., & Orshansky, M. (2013). Approximate computing: An emerging paradigm for energy-efficient th design. In Test Symposium (ETS), 2013 18 IEEE European (pp. 1-6). IEEE.
[4]. Kulkarni, P., Gupta, P., & Ercegovac, M. (2011). Trading accuracy for power with an under designed multiplier  architecture. In VLSI Design (VLSI Design), 2011 24th International Conference on (pp. 346-351). IEEE.
[5]. Kyaw, K. Y., Goh, W. L., & Yeo, K. S. (2010). Low-power high-speed multiplier for error-tolerant application. In Electron Devices and Solid-State Circuits (EDSSC), 2010 IEEE International Conference of (pp. 1-4). IEEE.
[6]. Labrado, C., Thapliyal, H., & Lombardi, F. (2017). Design of majority logic based approximate arithmetic circuits. In Circuits and Systems (ISCAS), 2017 IEEE International Symposium on (pp. 1-4). IEEE.
[7]. Lin, J. F., Hwang, Y. T., Sheu, M. H., & Ho, C. C. (2007). A novel high-speed and energy efficient 10-transistor full adder design. IEEE Transactions on Circuits and Systems Part 1 Regular Papers, 54(5), 1050.
[8]. Padmavathy, R. A., & Govindharajan. (2017). Design of combinational circuit using QcaSSRG. International Journal of Electronics and Communication Engineering, 73-80.
[9]. Schlachter, J., Camus, V., Palem, K. V., & Enz, C. (2017). Design and applications of approximate circuits by gate-level pruning. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 5, 1694-1702.
[10]. Verma, A. K., Brisk, P., & Ienne, P. (2008). Variable latency speculative addition: A new paradigm for arithmetic circuit design. In Proceedings of the Conference on Design, Automation and Test in Europe (pp. 1250-1255). ACM.
[11]. Vinitha, K., Dhanam, B., & Ramasamy, K. (2017). BCD adder design using approximate adder in quantumdot cellular automata. International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, 6(1), 47-57.
[12]. Yang, Z., Jain, A., Liang, J., Han, J., & Lombardi, F. (2013). Approximate XOR/XNOR-based adders for inexact computing. In Nanotechnology (IEEE-NANo),  2013 13th IEEE Conference on (pp. 690-693). IEEE.
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