Reversible Logic is the dominating field of research in low power Very-Large-Scale Integration (VLSI). In recent time, reversible logic has gained special attention in order to reduce power consumption mainly in concern to digital logic design. The main aim of this paper is to realize and synthesize shift counters like Ring counter and Johnson ring counter using reversible logic. Shift Counter is a sequential circuit that performs counting through shifting operation in a loop fashion. The output of last register of the circuit will be fed to the input of first register. Ring counter owns its applications in clock division circuits, square wave generators, hardware logic design of Application-Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA) circuits etc., Ring counter and Johnson Ring counter are designed using reversible logic to reduce power dissipation. A Boolean function f (i1 , i2 , i3 , ……, i n) having 'n' inputs and 'm' outputs is said to be logically reversible, if the number of inputs are equal to the number of outputs ( i.e. n = m) and the input pattern maps uniquely to the output pattern. Few reversible logic gates present in the literature are NOT gate, Feynman Gate (CNOT gate), Double Feynman Gate, Peres Gate, TR gate, Seynman Gate etc. The reversible gate must run both in forward and backward directions such that the inputs can be retrieved with the knowledge of outputs. The two limitations of logical reversibility are Fan-out and Feed-back are not allowed. Signals from required output lines are duplicated to desired lines using additional reversible combinational circuits to overcome the Fan-out limitation. Reversible Logic has applications in various fields like Quantum Computing, Optical Computing, Nanotechnology, Computer Graphics, Low power VLSI etc. Reversible logic has gained essence in recent years largely due to its property of low power consumption and low heat dissipation. In this paper, shift registers like shift right register and shift left register which have less heat dissipation and low power consumption is proposed. Till date, shift counters are not yet designed using reversible logic. In this paper, an attempt has been made to design shift counters like ring counter and Johnson ring counter using reversible logic. The designed circuits are analysed in terms of Quantum Cost (QC), Garbage Outputs (GO) and number of gates. The circuit has been designed and simulated using Xilinx software.
