Loss Distribution Methodology with a Sense Of Emission Dispatch
Low Power Optimization Technique Based Linear Feedback Shift Register
Leakage Power Reduction Using Multi Modal Driven Hierarchical Power Mode Switches
Validation of IOV chain using OVM Technique
Performance of Continuous and Discontinuous Space Vector Pwm Technique for Open End Winding Induction Motor Drive
Electronic Circuit Design for Electromagnetic Compliance through Problem-Based Learning
Trioinformatics: The Innovative and Novel Logic Notation That Defines, Explains, and Expresses the Rational Application of The Law of Trichotomy for Digital Instrumentation and Circuit Design
Design Of a Novel Gated 5T SRAM Cell with Low Power Dissipation in Active and Sleep Mode
A Two Stage Power Optimized Implantable Neural Amplifier Based on Cascoded Structures
An Efficient Hybrid PFSCL based Implementation of Asynchronous Pipeline
Increasing applications of constantly developing electronic devices require delicate voltage and current protection. Although the electrical network is monitored continuously, undesired over currents and over voltages may occur on the distribution system due to failures. Most of the electronic switch gear is connected via surge protected power strips in indoor applications, where current protection is vital. Surge protected power strips are usually manufactured based on Metal Oxide Varistors (MOVs) which are capable of executing extremely non-linear current voltage characteristics. MOVs are employed for absorbing surges in the network and maintain acceptable current readings on the terminals of the power strip. Generally, MOV protected systems are analysed for transient surges within limited time durations. In this study, commercially available surge protected power strips are subjected to continuous over voltages in contrast to rated voltages and current and voltage characteristics are investigated. Besides, generated harmonics of surge protected power strips are analysed under extreme voltage conditions and maximum endurance of these strips are revealed.
An Arithmetic and Logic Unit (ALU) is an advanced circuit that performs number-crunching and rationale operations. ALU is an essential building piece of the focal preparing unit of a PC. The power, devoured by the ALU has a direct effect on the power disseminated from the processor. Thus, a plan is required to execute the ALU in a manner, where the execution of the processor is enhanced and furthermore the power devoured is less. An ALU utilizing 8T Full Adder with FinFETs as a customary technique. In customary, ALU devours a lot of energy. The proposed ALU outlined utilizing 8T Full Adder with a FinFETs. It has an intense control on short channel impacts while downsizing the measure of the transistor. The outline recreation is done in CADENCE IC 12.1 Tool. At long lasting power has been considered and furthermore contrasted between the Exiting ALU plan and proposed FinFET based outline of the ALU.
Power dissipation is an important parameter in VLSI circuits. Previously it was ignored due to low device density and low operating frequency. Due to the challenging issues on high packing density, high operating frequency and increase in portable consumer electronics, high heat dissipation occurs which damages the performance. The previous method using 1 bit full adder was not sufficient in handling high performance circuit. The proposed method reduces the power dissipation of a device and at the same time maintains an adequate throughput. For any processor, Full Adder is an important block for all processing and execution of mathematical models. By using Pass Transistor Logic (PTL) redundant transistors can be eliminated which in turn increases the speed and reduces the heat. The proposed method of including NMOS based PTL increases the performance of 1 bit and 8 bit full adder with more transistors in low area for an efficient power handling method. The results of the proposed work is compared with XOR existing method. The proposed full adder is efficient in terms of power, area.
This paper proposed a high level novel cascaded multilevel inverter which has less number of switches and less number of sources. Generally, industries are used high level multilevel inverters for meeting large power demand. In order to get quality output voltage, authors required multilevel inverters than conventional inverters. In this paper, an authors proposed new structure of sub multilevel inverter with less number of switches and less number of DC sources. A high level novel cascaded multilevel inverter is proposed, which is cascaded combination of newly proposed sub multilevel inverters. Over all number of switches is less in proposed high level novel multilevel inverter. This novel high level cascaded multilevel inverter is implemented in symmetrical as well as asymmetrical forms. The optimal structure is possible with asymmetrical form which has fewer switches, less sources and less standing voltages than symmetrical form. The proposed topology is compared with respect to existing topology such as cascaded H bridge by considering number of components such as number of switches and IGBTs, etc. This proposed high level novel multilevel inverter is verified with computer simulation.
Binary Addition is one of the most important arithmetic operation that a processor can execute. Such ALU process requires to be operated with high speed without degrading the performance of the circuit. Since VLSI mainly focus in area, delay and power consumption, a good VLSI circuit can maintain tradeoff between these parameters. In this paper, parallel Self Timed Adder is presented, which is capable of performing multipath binary addition. This parallel operation do not generate carry chain propagations thereby speedup the circuitry. One advantage of parallel adder is it maintains the tradeoff between Fan-in and Fan-out by incorporating suitable transistors in parallel. The design is implemented in Xilinx ISE14.2 synthesis tool with Virtex-5 FPGA as the target hardware equipment. For backend analysis, the XOR gate and multiplexers are designed by using extended Dual Mode Logic Technique and layouts are designed in Microwind3.1 at 32 nm CMOS Technology The simulation and synthesis results reveals the fact the parallel self timed adder have the potential to run faster when compared with existing asynchronous adder.
This paper presents a reaching condition methods for Sliding Mode Controlled DC-DC Buck Converter. Three approaches are specified for reaching conditions. The approaches comparing among the chattering, which is effectively reduced the chattering and fast speed is kept. The approaches are direct switching, lyapunov and reaching law approach. Among them reaching law approach minimizes the chattering and effective output is obtained. Various output voltages are obtained by keeping V as constant and chattering is analysed, minimized and also takes very less ref time to reach the steady state. A simulation results shows better reduction of chattering by the reaching law.
