Loss Distribution Methodology with a Sense Of Emission Dispatch
Low Power Optimization Technique Based Linear Feedback Shift Register
Leakage Power Reduction Using Multi Modal Driven Hierarchical Power Mode Switches
Validation of IOV chain using OVM Technique
Performance of Continuous and Discontinuous Space Vector Pwm Technique for Open End Winding Induction Motor Drive
Electronic Circuit Design for Electromagnetic Compliance through Problem-Based Learning
Trioinformatics: The Innovative and Novel Logic Notation That Defines, Explains, and Expresses the Rational Application of The Law of Trichotomy for Digital Instrumentation and Circuit Design
Design Of a Novel Gated 5T SRAM Cell with Low Power Dissipation in Active and Sleep Mode
A Two Stage Power Optimized Implantable Neural Amplifier Based on Cascoded Structures
An Efficient Hybrid PFSCL based Implementation of Asynchronous Pipeline
Today's major challenge in designing electronic circuits is to deliver high-performance with minimal power dissipation. While electronic devices have achieved tremendous improvement in performance and area reduction over the last decade, as a consequence the power dissipation has increased many folds. Adiabatic logic style is a promising technique aimed at building energy-efficient devices at a structural level. A linear feedback shift register (LFSR) is a circuit extensively used for pseudo-random number generation, which finds applications in cryptography and circuit testing. An LFSR dissipates high dynamic power in its operation and is, therefore, an excellent candidate to evaluate the benefits of using the adiabatic logic style for power reduction versus the conventional CMOS logic style. Various adiabatic logic families exist; their structures mainly differ in the presence or absence of diodes. In this paper, an LFSR based pseudo-random number generator is implemented using popular adiabatic logic families like Two-Phase Adiabatic Static CMOS Logic (2PASCL), which uses diodes and other diode-free adiabatic logic styles like Clocked CMOS Adiabatic Logic (CCAL) and Diode-Free Adiabatic Logic (DFAL). A comparison of these implementations is made for power consumption, time delay and Power-Delay Product (PDP) with the conventional CMOS logic style, substantiating the superiority of the adiabatic logic families in terms of power and PDP. The suitability of these adiabatic logic families is also evaluated for different applications. The simulations are carried out on TANNER EDA TSPICE using 0.18 micron CMOS technology BSIMv3.1 parameters.
In this paper, new type of single input and three output universal filters with current conveyor as an active element is proposed. Current conveyor works similar to operational amplifier but the input and output signals are current rather than voltage. There are several types of current conveyors exist. Out of the existing, Second order current conveyor (CCII) is chosen as an active element. The proposed circuits are designed using the similar type of active element and grounded passive components. The detailed mathematical analysis is carried out. The necessary expressions for quality factor and sensitivity are also derived. The responses of High pass filter, Low pass filter and Band pass filter are measured simultaneously. The notch and all pass filters can also be realized by adding the appropriate components. All simulation work is carried out with MULTISIM 13.0. The comparative analysis is carried out with the existing techniques and is tabulated. It has been observed that the proposed circuits works good in comparison with the existing topologies.
The aim of this study is to implement better heuristics in solving the issue of hysteresis in design of an automatic voltage regulator to bring significant precision and resolution. In rural areas, voltage provided continues to be lesser than specified that does not provide the necessary feed to the electronic circuits where it may be required. This puts sophisticated electronic devices such as computers and other devices at substantial risk. In this proposed work simulated the entire automatic voltage regulator section in Multisim is simulated and hereby proposed a signal conditioning circuit that can resolve the issue of identifying the role of a linear circuit design and a small signal analyzer for amplitude frequency characteristics. In order to restore this circumstance, this research identifies the mechanism for stabilizing a diverse range of input voltage from the lowest to the highest value by discussing a measuring circuit that drives the transformer from either the main side to the secondary side repeatedly. This study therefore proposes an alternative solution by developing an Automatic Voltage Regulator (AVR) involving design of different controllers and systems that operate within the monitoring range. The digital AVR requires certain computational modifications based on certain parameters and features.
This paper presents the concepts of three phase matrix converter based power electronic transformer for electric traction applications. The proposed high frequency Power Electronic Transformer (PET) will regulate the voltage level of the crossing train. The power electronic transformer with three phase matrix converter is used to step up frequency at the primary side and single phase matrix converter is to step down frequency at the secondary side for catenary. Power Electronic Transformer has several advantages over conventional solid state 50 Hz transformer. The control technique adopted is Space Vector Modulation (SVM) Technique for three phase matrix converter and Sinusoidal Pulse Width Modulation (SVM) for single phase matrix converter. The results of the Power Electronic Transformer along with the filters have been presented in this paper. The proposed topology has been implemented in the MATLAB/SIMULINK software and the desired results of the converter topology were verified.
This paper proposes Fuzzy Logic controller (FLC) based on Dynamic Voltage Restorer (DVR) Controller along with Directquadrature- zero (dq0) transformation for power quality improvement in a distribution system. Distribution needs protection against the power quality problems like Sag and Swell for providing good supply at the load. Sag and Swell can be compensated by injecting the compensating voltage method using Dynamic Voltage Restorer (DVR). In this research work, DVR is used for the improvement of power quality in distribution systems by using SPWM and SVPWM techniques. Total Harmonic Distribution (THD) and Power Factor (PF) values are compared for both the conditions with and without PI and FLC. The desired compensations are confirmed by the results of the simulation in MATLAB / SIMULINK Software.
