Today's major challenge in designing electronic circuits is to deliver high-performance with minimal power dissipation. While electronic devices have achieved tremendous improvement in performance and area reduction over the last decade, as a consequence the power dissipation has increased many folds. Adiabatic logic style is a promising technique aimed at building energy-efficient devices at a structural level. A linear feedback shift register (LFSR) is a circuit extensively used for pseudo-random number generation, which finds applications in cryptography and circuit testing. An LFSR dissipates high dynamic power in its operation and is, therefore, an excellent candidate to evaluate the benefits of using the adiabatic logic style for power reduction versus the conventional CMOS logic style. Various adiabatic logic families exist; their structures mainly differ in the presence or absence of diodes. In this paper, an LFSR based pseudo-random number generator is implemented using popular adiabatic logic families like Two-Phase Adiabatic Static CMOS Logic (2PASCL), which uses diodes and other diode-free adiabatic logic styles like Clocked CMOS Adiabatic Logic (CCAL) and Diode-Free Adiabatic Logic (DFAL). A comparison of these implementations is made for power consumption, time delay and Power-Delay Product (PDP) with the conventional CMOS logic style, substantiating the superiority of the adiabatic logic families in terms of power and PDP. The suitability of these adiabatic logic families is also evaluated for different applications. The simulations are carried out on TANNER EDA TSPICE using 0.18 micron CMOS technology BSIMv3.1 parameters.