Loss Distribution Methodology with a Sense Of Emission Dispatch
Low Power Optimization Technique Based Linear Feedback Shift Register
Leakage Power Reduction Using Multi Modal Driven Hierarchical Power Mode Switches
Validation of IOV chain using OVM Technique
Performance of Continuous and Discontinuous Space Vector Pwm Technique for Open End Winding Induction Motor Drive
Electronic Circuit Design for Electromagnetic Compliance through Problem-Based Learning
Trioinformatics: The Innovative and Novel Logic Notation That Defines, Explains, and Expresses the Rational Application of The Law of Trichotomy for Digital Instrumentation and Circuit Design
Design Of a Novel Gated 5T SRAM Cell with Low Power Dissipation in Active and Sleep Mode
A Two Stage Power Optimized Implantable Neural Amplifier Based on Cascoded Structures
An Efficient Hybrid PFSCL based Implementation of Asynchronous Pipeline
In this paper, a novel methodology with load flow implementation has been presented to remove extra burden on slack bus in emission aspect. Using this methodology, the effect of nature of power plant (Thermal/Gas) has been analyzed on the system objectives. Optimal Unfied Power Flow Controller (OUPFC) is incorporated in the system for the power flow control. As this methodology works independent of the size and nature of the system, it can be applicable for any type of system. The complete methodology has been tested on IEEE-14 bus test system with supporting numerical and graphical results.
n this paper, an efficient Distributed Arithmetic (DA) based reconfigurable Finite Impulse Response (FIR) digital filter is presented which is designed to yield high performance and throughput. To achieve this, the FIR filter co-efficients are designed to change automatically during the processing time. The primary hardware component in the DA based FIR filter is Look-up-Tables (LUTs). In existing architecture to design a filter, RAM based LUTs are used which is not practical for implementing the design as the arithmetic processing partial products are stored in the RAM that thereby consumes more memory blocks. Other limitation of RAM based DA is the structure. It is more cost effective to implement the design in ASIC. To overcome this limitation, shared LUTs are proposed, where instead of storing all the partial inner products in the RAM, shared registers are used to store the bit positions based on the weightage, thereby reducing the use of hardware components when compared with the CSA based structure. The proposed design has less Area-Delay product and less energy per sample. Simulation and synthesis results are verified by using Xilinx 14.2 synthesis tool and Virtex-5 FPGA is the target device. The experimental results show that the proposed design is more efficient than the previous works.
One of the most promising and emerging technologies in the low power VLSI is reversible logic computing, which has found its voluminous applications in nanotechnology, Quantum computing (Feynman,1986), and Quantum Dot Cellular Automata (QCA). This study presents high-speed reversible carry skip adder and carry skip BCD adder. The performance analyses of proposed architectures are mainly focused on the delay and almost all the previous existing designs are not concentrated on the delay. In this paper, both the proposed design architectures are highly optimized in terms of delay. The complete simulation and synthesis process is carried out by using the Xilinx ISE 14.7 and it is dumped on the FPGA Spartan-6.
In Very-Large-Scale Integration (VLSI), the main challenges for the researchers are to reduce the power dissipation by the devices. In this paper, the authors have proposed a modified version of the Linear Feedback Shift Register to meet the specific output. The power consumption can be reduced by deactivating the clock signal from the flip flop to design test pattern generator during testing power. The LFSR pseudo-random test pattern generator is used in the testing of the ASIC chips, which is used to generate the random sequences of the desired pattern generator. This paper will help in the reduction of additional test inputs used for the ASIC. The test pattern is generated in such a way that the component requirements can be reduced.
In this paper, various Low Power SRAM cell design techniques have been reviewed on the basis of power, stability, and delay. Many studies have proposed various SRAM architectures for different applications. It has been reported that 6T SRAM cell are high in speed but at low supply voltage, stability is a critical issue. It is found that 8T SRAM cell shows the highest level of stability at low supply voltage, but it has area penalty. Hence in this work all the required performance parameters of various SRAM cell architectures have been reviewed. This work will be helpful for VLSI designer to choose proper memory architecture as per applications. For example, machine learning needs high performance memory block while bio-medical implants require low power memory block. This paper also presents various tradeoffs between various design parameters of SRAM.
