i-manager Publications

i-manager's Journal on Circuits and Systems (JCIR)

Current Issue Vol. 11 Issue 2

Voltage Stability and Power Loss Minimization with UPFC using Heuristic and Hybrid Heuristic Methods
Design and Analysis of Voltage Difference Transconductance Amplifier (VDTA) at FINFET CMOS Technology
Efficient Logic Cell Design for Ultralow-Energy Subthreshold Operation in Wearable Biomedical Systems
Design and Optimization of MSI-Enabled Multi-Precision Binary Multiplier Architecture
Analysis of Carbon Nanotube for Low Power Nano Electronics Applications

Most Cited

Volume 6 Issue 1 December - February 2018

Research Paper

Loss Distribution Methodology with a Sense Of Emission Dispatch

Srilatha Dande* , Sivanagaraju Sirigiri**

* Research Scholar, JNT University, Kakinada, Andhra Pradesh, India.

** Professor, Department of Electrical and Electronics Engineering, University College of Engineering, JNT University, Kakinada, Andhra Pradesh, India

Dande, S., and Sirigiri, S. (2018). Loss Distribution Methodology With A Sense Of Emission Dispatch. i-manager’s Journal on Circuits and Systems, 6(1), 1-9. https://doi.org/10.26634/jcir.6.1.14037

Abstract

In this paper, a novel methodology with load flow implementation has been presented to remove extra burden on slack bus in emission aspect. Using this methodology, the effect of nature of power plant (Thermal/Gas) has been analyzed on the system objectives. Optimal Unfied Power Flow Controller (OUPFC) is incorporated in the system for the power flow control. As this methodology works independent of the size and nature of the system, it can be applicable for any type of system. The complete methodology has been tested on IEEE-14 bus test system with supporting numerical and graphical results.

References

[1]. Alvarado, F. L. (1978). Penalty factors from Newton's method. IEEE Transactions on Power Apparatus and Systems, (6), 2031-2040.

[2]. Duong, T., JianGang, Y., & Truong, V. (2013). A new method for secured optimal power flow under normal and network contingencies via optimal location of TCSC. International Journal of Electrical Power & Energy Systems, 52, 68-80.

[3]. Hazarika, D., & Bordoloi, P. K. (1991). Modified loss coefficients in the determination of optimum generation scheduling. In IEE Proceedings C (Generation, Transmission and Distribution) (Vol. 138, No. 2, pp. 166-172). IET Digital Library.

[4]. Jang, G. S., Hur, D., Park, J. K., & Lee, S. H. (2005). A modified power flow analysis to remove a slack bus with a sense of economic load dispatch. Electric Power Systems Research, 73(2), 137-142.

[5]. Jiang, A., & Ertem, S. (1995). Polynomial loss models for economic dispatch and error estimation. IEEE Transactions on Power Systems, 10(3), 1546-1552.

[6]. Mandal, B., Roy, P. K., & Mandal, S. (2014). Economic load dispatch using krill herd algorithm. International Journal of Electrical Power & Energy Systems, 57, 1-10.

[7]. Okamura, M., O-ura, Y., Hayashi, S., Uemura, K., & Ishiguro, F. (1975). A new power flow model and solution method including load and generator characteristics and effects of system control devices. IEEE Transactions on Power Apparatus and Systems, 94(3), 1042-1050.

[8]. Park, Y. M., Lee, J. H., & Newton, A. (1993). Raphson load flow considering frequency characteristics. Korean Inst. Electrical Eng., 42, 85-93.

[9]. Roy, P., Roy, P., & Chakrabarti, A. (2013). Modified shuffled frog leaping algorithm with genetic algorithm crossover for solving economic load dispatch problem with valve-point effect. Applied Soft Computing, 13(11), 4244- 4252.

[10]. Shin, J. R., & Yim, H. S. (1993). An extended approach for NR load flow with power loss correction method. In TENCON'93. Proceedings. Computer, Communication, Control and Power Engineering. 1993 IEEE Region 10 Conference on (Vol. 5, pp. 402-405). IEEE.

[11]. Zhan, J. P., Wu, Q. H., Guo, C. X., & Zhou, X. X. (2014). Fast-Iteration Method for Economic Dispatch With Prohibited Operating Zones. IEEE Transactions on Power Systems, 29(2), 990-991.

[12]. Zhan, J., Wu, Q. H., Guo, C., & Zhou, X. (2015). Economic dispatch with non-smooth objectives-part I: Local minimum analysis. IEEE Transactions on Power Systems, 30(2), 710-721.

[13]. Zhong, H., Xia, Q., Wang, Y., & Kang, C. (2013). Dynamic economic dispatch considering transmission losses using quadratically constrained quadratic program method. IEEE Transactions on Power Systems, 28(3), 2232- 2241.

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Research Paper

VLSI Design of High Performance DA-Based Reconfigurable FIR Digital Filter For ASIC and FPGA Implementation

P. Lokesh* , S.Chandana , U.Somalatha *

*-*** Assistant Professor, Department of Electronics and Communication Engineering, VEMU Institute of Technology, P. Kothakota, India.

Lokesh, P., Chandana, S., and Somalatha, U. (2018). VLSI Design Of High Performance DA-Based Reconfigurable FIR Digital Filter For ASIC and FPGA Implementation. i-manager’s Journal on Circuits and Systems, 6(1), 8-13. https://doi.org/10.26634/jcir.6.1.14494

Abstract

n this paper, an efficient Distributed Arithmetic (DA) based reconfigurable Finite Impulse Response (FIR) digital filter is presented which is designed to yield high performance and throughput. To achieve this, the FIR filter co-efficients are designed to change automatically during the processing time. The primary hardware component in the DA based FIR filter is Look-up-Tables (LUTs). In existing architecture to design a filter, RAM based LUTs are used which is not practical for implementing the design as the arithmetic processing partial products are stored in the RAM that thereby consumes more memory blocks. Other limitation of RAM based DA is the structure. It is more cost effective to implement the design in ASIC. To overcome this limitation, shared LUTs are proposed, where instead of storing all the partial inner products in the RAM, shared registers are used to store the bit positions based on the weightage, thereby reducing the use of hardware components when compared with the CSA based structure. The proposed design has less Area-Delay product and less energy per sample. Simulation and synthesis results are verified by using Xilinx 14.2 synthesis tool and Virtex-5 FPGA is the target device. The experimental results show that the proposed design is more efficient than the previous works.

References

[1]. Chen, K. H., & Chiueh, T. D. (2006). A low-power digitbased reconfigurable FIR filter. IEEE Transactions on Circuits and Systems II: Express Briefs, 53(8), 617-621. .

[2]. Dempster, A. G., & Macleod, M. D. (1995). Use of minimum-adder multiplier blocks in FIR digital filters. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 42(9), 569-577

[3]. Hatai, I., Chakrabarti, I., & Banerjee, S. (2013). Reconfigurable architecture of a RRC FIR interpolator for multi-standard digital up converter. In Parallel and Distributed Processing Symposium Workshops & PhD Forum th (IPDPSW), 2013 IEEE 27 International (pp. 247-251). IEEE.

[4]. Hentschel, T., Henker, M., & Fettweis, G. (1999). The digital front-end of software radio terminals. IEEE Personal Communications, 6(4), 40-46.

[5]. Kumm, M., Möller, K., & Zipf, P. (2013). Dynamically reconfigurable FIR filter architectures with fast reconfiguration. In Reconfigurable and Communication- Centric Systems-on-Chip (ReCoSoC), 2013 8 International Workshop on (pp. 1-8). IEEE.

[6]. Meher, P. K. (2006). Hardware-efficient systolization of DA-based calculation of finite digital convolution. IEEE Transactions on Circuits and Systems II: Express Briefs, 53(8), 707-711.

[7]. Meher, P. K., Chandrasekaran, S., & Amira, A. (2008). FPGA realization of FIR filters by efficient and flexible systolization using distributed arithmetic. IEEE Transactions on Signal Processing, 56(7), 3009-3017.

[8]. Ming, L., & Chao, Y. (2012). The multiplexed structure of multi-channel FIR filter and its resources evaluation. In Computer Distributed Control and Intelligent Environmental Monitoring (CDCIEM), 2012 International Conference on (pp. 764-768). IEEE.

[9]. Ozalevli, E., Huang, W., Hasler, P. E., & Anderson, D. V. (2008). A reconfigurable mixed-signal VLSI implementation of distributed arithmetic used for finite-impulse response filtering. IEEE Transactions on Circuits and Systems I: Regular Papers, 55(2), 510-521.

[10]. White, S. A. (1989). Applications of distributed arithmetic to digital signal processing: A tutorial review. IEEE Assp Magazine, 6(3), 4-19.

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Research Paper

FPGA Implementation of Reversible High-Speed Carry Skip Adder and Carry Skip BCD Adder

K. Rajesh * , G. Umamaheswara Reddy**

* Research Scholar, Department of Electronics and Communication Engineering, Sri Venkateswara University, Tirupati, Andhra Pradesh, India.

** Professor, Department of Electronics and Communication Engineering, Sri Venkateswara University, Tirupati, Andhra Pradesh, India.

Rajesh, K., and Reddy, G. U. (2018). FPGA Implementation of Reversible High-Speed Carry Skip Adder and Carry Skip BCD Adder. i-manager’s Journal on Circuits and Systems, 6(1), 14-19. https://doi.org/10.26634/jcir.6.1.14496

Abstract

One of the most promising and emerging technologies in the low power VLSI is reversible logic computing, which has found its voluminous applications in nanotechnology, Quantum computing (Feynman,1986), and Quantum Dot Cellular Automata (QCA). This study presents high-speed reversible carry skip adder and carry skip BCD adder. The performance analyses of proposed architectures are mainly focused on the delay and almost all the previous existing designs are not concentrated on the delay. In this paper, both the proposed design architectures are highly optimized in terms of delay. The complete simulation and synthesis process is carried out by using the Xilinx ISE 14.7 and it is dumped on the FPGA Spartan-6.

References

[1]. Ali, M. D. B., Rahman, M. D. S., & Parvin, T. (2012). Optimized design of carry skip BCD adder using new FSNG reversible logic gates. IJCSI Int. J. Comput. Sci., 9(4), 424-431.

[2]. Babu, H. M. H., & Chowdhury, A. R. (2005). Design of a reversible binary coded decimal adder by using reversible 4-bit parallel adder. In VLSI Design, 2005. 18^th International Conference on (pp. 255-260). IEEE

[3]. Bennett, C. H. (1973). Logical reversibility of computation. IBM Journal of Research and Development, 17(6), 525-532.

[4]. Bhagyalakshmi, H. R., & Venkatesha, M. K. (2011). Optimized design of BCD adder and Carry skip BCD adder using reversible logic gates. International Journal on Computer Science and Engineering, 3(4), 1439-1449.

[5]. Biswas, A. K., Hasan, M. M., Hasan, M., Chowdhury, A. R., & Babu, H. M. H. (2008). A novel approach to design BCD adder and Carry Skip BCD adder. In VLSI Design, 2008. VLSID 2008. 21^stInternational Conference on (pp. 566- 571). IEEE.

[6]. Biswas, A. K., Hasan, M. M., Hasan, M., Chowdhury, A. R., & Babu, H. M. H. (2008). A novel approach to design BCD adder and Carry Skip BCD adder. In VLSI Design, 2008. st VLSID 2008. 21^st International Conference on (pp. 566- 571). IEEE.

[7]. Bruce, J. W., Thornton, M. A., Shivakumaraiah, L., Kokate, P. S., & Li, X. (2002). Efficient adder circuits based on a conservative reversible logic gate. In VLSI, 2002. Proceedings. IEEE Computer Society Annual Symposium on (pp. 83-88). IEEE.

[8]. Devi, N. S., Prasad, B. S., & Sravani, N. (2015). Effective Design and Implementation of Reversible BCD Adder. International Journal of Advanced Technology and Research Innovative, 7(15), 2994-2998.

[9]. Feynman, R. P. (1986). Quantum mechanical computers. Foundations of Physics, 16(6), 507-531.

[10]. Fredkin, E., & Toffoli, T. (1982). Conservative logic. International Journal of Theoretical Physics, 21(3-4), 219- 253.

[11]. Islam, M. S., Rahman, M. M., Begum, Z., & Hafiz, M. Z. (2009). Fault tolerant reversible logic synthesis: Carry lookahead and carr y-skip adders. In Advances in Computational Tools for Engineering Applications, 2009. ACTEA'09. International Conference on (pp. 396-401). IEEE.

[12]. Islam, M., & Begum, Z. (2010). Reversible logic synthesis of fault tolerant carry skip BCD adder. arXiv preprint arXiv:1008.3288, 32(2), 234-250

[13]. Lala, P. K., Parkerson, J. P., & Chakraborty, P. (2010). Adder designs using reversible logic gates. WSEAS Transactions on Circuits and Systems, 9(6), 369-378.

[14]. Peres, A. (1985). Reversible logic and quantum computers. Physical Review A, 32(6), 3266-3276.

[15]. Rajesh, K., & Tatajee, D. A. (2012). An optimized BCD adder using reversible logic gates. International Journal of Modern Engineering Research, 2(6), 4527-4531

[16]. Thapliyal, H., Kotiyal, S., & Srinivas, M. B. (2006, January). Novel BCD adders and their reversible logic implementation for IEEE 754r format. In VLSI Design held jointly with 5^th International Conference on Embedded Systems Design, 19^th International Conference on (pp. 6). IEEE.

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Review Paper

Low Power Optimization Technique Based Linear Feedback Shift Register

Dharmendra Singh* , Ankit Singh, Prachi Agrawal*, Harshita Agrawal****

- Assistant Professor, Department of Electronics and Telecommunication Engineering, SSIPMT, Raipur, India.

-**** UG Scholar, Department of Electronics and Telecommunication Engineering, SSIPMT, Raipur, India.

Singh, D., Singh, A., Agrawal, P., and Agrawal, H. (2018). Low Power Optimization Technique Based Linear Feedback Shift Register. i-manager’s Journal on Circuits and Systems, 6(1), 20-24. https://doi.org/10.26634/jcir.6.1.14058

Abstract

In Very-Large-Scale Integration (VLSI), the main challenges for the researchers are to reduce the power dissipation by the devices. In this paper, the authors have proposed a modified version of the Linear Feedback Shift Register to meet the specific output. The power consumption can be reduced by deactivating the clock signal from the flip flop to design test pattern generator during testing power. The LFSR pseudo-random test pattern generator is used in the testing of the ASIC chips, which is used to generate the random sequences of the desired pattern generator. This paper will help in the reduction of additional test inputs used for the ASIC. The test pattern is generated in such a way that the component requirements can be reduced.

References

[1]. Ahmed, N., Tehranipour, M. H., & Nourani, M. (2004). Low power pattern generation for BIST architecture. In Circuits and Systems, 2004. ISCAS'04. Proceedings of the 2004 International Symposium on (Vol. 2, pp. II-689-92). IEEE.

[2]. Ajane, A., Furth, P. M., Johnson, E. E., & Subramanyam, R. L. (2011). Comparison of binary and LFSR counters and efficient LFSR decoding algorithm. In Circuits and Systems th (MWSCAS), 2011 IEEE 54 International Midwest Symposium on (pp. 1-4). IEEE.

[3]. Brock, T. B. (2006). Linear Feedback Shift Registers in SAGE, 1-18.

[4]. Gunavathi, K., Paramasivam, K., Lavanya, P. S., & Umamageswaran, M. (2006). A novel BIST TPG for testing of VLSI circuits. In Industrial and Information Systems, First International Conference on (pp. 109-114). IEEE.

[5]. Haridas, N., & Devi, M. N. (2011). Modified Genetic Algorithm for Deciding LFSR Configuration, 2(2), 34-36.

[6]. Kaur, R., & Baja, N. (2012). Enhancement in Feedback Polynomials of LFSR used in A5/1 Stream Cipher. International Journal of Computer Applications, 57(19), 32-35.

[7]. Muttoo, S. K., & Abdulsattar, I. (2012). A new stegosystem based on LFSR generator. International Journal of Engineering and Innovative Technology (IJEIT), 1(1), 40-43.

[8]. Prasada Rao, R. V., Varaprasad, N. A., Babu, G. S., & Mohan, C. M. (2013). Power Optimization of Linear Feedback Shift Register (LFSR) for Low Power BIST implemented in HDL. International Journal of Modern Engineering Research (IJMER), 3(3), 1523-1528.

[9]. Tehranipoor, M., Nourani, M., & Ahmed, N. (2005). Low transition LFSR for BIST-based applications. In Test th Symposium, 2005. Proceedings. 14 Asian (pp. 138-143). IEEE.

[10]. Zeng, G., Han, W., & He, K. (2007). High Efficiency Feedback Shift Register: Sigma-LFSR. IACR Cryptology ePrint Archive, 2007, 114.

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Research Paper

Performance Parameters of Low Power SRAM cells: A Review

Nidhi Tiwari* , Vaibhav Neema, Kamal J Rangra*, Yogesh Chandra Sharma****

* Research Scholar, Department of Electronics and Communication Engineering, Vivekananda Global University, Jaipur, India.

Assistant Professor, Department of Electronics and Communication Engineering, Institute of Engineering and Technology, Devi Ahilya University, Indore, India.

* Chief Scientist, Transducers and Actuators Group, CSIR-CEERI, Pilani, India.

**** Professor, Department of Physics, Vivekananda Global University, Jaipur, India.

Tiwari, N., Neema, V., Rangra, K. J., and Sharma, Y. C. (2018). Performance Parameters of Low Power SRAM cells: A Review. i-manager’s Journal on Circuits and Systems, 6(1), 25-34. https://doi.org/10.26634/jcir.6.1.14495

Abstract

In this paper, various Low Power SRAM cell design techniques have been reviewed on the basis of power, stability, and delay. Many studies have proposed various SRAM architectures for different applications. It has been reported that 6T SRAM cell are high in speed but at low supply voltage, stability is a critical issue. It is found that 8T SRAM cell shows the highest level of stability at low supply voltage, but it has area penalty. Hence in this work all the required performance parameters of various SRAM cell architectures have been reviewed. This work will be helpful for VLSI designer to choose proper memory architecture as per applications. For example, machine learning needs high performance memory block while bio-medical implants require low power memory block. This paper also presents various tradeoffs between various design parameters of SRAM.

References

[1]. Akashe, S., Tiwari, N. K., & Sharma, R. (2012). Simulation and stability analysis of 6T and 9T SRAM cell in 45 nm era. In nd Power, Control and Embedded Systems (ICPCES), 2012 2 International Conference on (pp. 1-6). IEEE.

[2]. Alorda, B., Carmona, C., Torrens, G., & Bota, S. (2016). An affordable experimental technique for SRAM write margin characterization for nanometer CMOS technologies. Microelectronics Reliability, 65, 280-288.

[3]. Butzen, P. F., & Ribas, R. P. (2006). Leakage current in submicrometer CMOS gates. Universidade Federal do Rio Grande do Sul, 1-28.

[4]. Farkhani, H., Peiravi, A., & Moradi, F. (2015). A new write assist technique for SRAM design in 65 nm CMOS technology. Integration, the VLSI Journal, 50, 16-27.

[5]. Hazucha, P., Karnik, T., Maiz, J., Walstra, S., Bloechel, B., Tschanz, J., ... & Borkar, S. (2003). Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-/spl mu/m to 90-nm generation. In Electron Devices Meeting, 2003. IEDM'03 Technical Digest. IEEE International (pp. 21-5). IEEE.

[6]. Hoffmann, K. (1982). Status and trends of dynamic and static RAMs. Microprocessing and Microprogramming, 10(2-3), 119-127. .

[7]. Jiao, H., & Kursun, V. (2010). Tri-mode operation for noise reduction and data preservation in low-leakage multi-threshold CMOS circuits. In IFIP/IEEE International Conference on Very Large Scale Integration-System on a Chip (pp. 258-290). Springer, Berlin, Heidelberg.

[8]. Jiao, H., Qiu, Y., & Kursun, V. (2016a). Low power and robust memory circuits with asymmetrical ground gating. Microelectronics Journal, 48, 109-119.

[9]. Jiao, H., Qiu, Y., & Kursun, V. (2016b). Variability-aware 7T SRAM circuit with low leakage high data stability SLEEP mode. Integration, the VLSI Journal, 53, 68-79.

[10]. Kang, S. M., & Leblebici, Y. (2003). CMOS Digital Integrated Circuits: Analysis and Design. Tata Mcgraw-Hill.

[11]. Khare, K., Khare, N., Kulhade, V. K., & Deshpande, P. (2008). VLSI design and analysis of low power 6T SRAM cell using cadence tool. In Semiconductor Electronics, 2008. ICSE 2008. IEEE International Conference on (pp. 117-121). IEEE

[12]. Kim, J., & Mazumder, P. (2017). A robust 12T SRAM cell with improved write margin for ultra-low power applications in 40nm CMOS. Integration, the VLSI Journal, 57, 1-10.

[13]. Margala, M. (1999). Low-power SRAM circuit design. In Memory Technology, Design and Testing, 1999. Records of the 1999 IEEE International Workshop on (pp. 115-122). IEEE.

[14]. Predictive Technology Model (PTM). Retrieved from http://www.eas.asu.edu/_ptm/

[15]. Shrivas, J., & Akashe, S. (2012). Impact of Design Parameter on SRAM Bit Cell. In Advanced Computing & Communication Technologies (ACCT), 2012 Second International Conference on (pp. 353-356). IEEE.

[16]. Siebel, O. F., Schneider, M. C., & Galup-Montoro, C. (2012). MOSFET threshold voltage: Definition, extraction, and some applications. Microelectronics Journal, 43(5), 329-336.

[17]. Tanaka, C., Saitoh, M., Ota, K., & Numata, T. (2015). Analysis of static noise margin improvement for low voltage SRAM composed of nano-scale MOSFETs with ideal subthreshold factor and small variability. Solid-State Electronics, 109, 58-62.

[18]. Upadhyay, P., Kar, R., Mandal, D., & Ghoshal, S. P. (2015). A design of low swing and multi threshold voltage based low power 12T SRAM cell. Computers & Electrical Engineering, 45, 108-121.

[19]. Wang, B., Zhou, J., & Kim, T. T. H. (2015). SRAM devices and circuits optimization toward energy efficiency in multith V CMOS. Microelectronics Journal, 46(3), 265-272.

[20]. Wang, X., Zhang, Y., Lu, C., & Mao, Z. (2016). Power efficient SRAM design with integrated bit line charge pump. AEU- International Journal of Electronics and Communications, 70(10), 1395-1402.

[21]. Wu, S. L., Lu, C. Y., Tu, M. H., Huang, H. S., Lee, K. D., Kao, Y. S., & Chuang, C. T. (2016). A 0.35 V, 375 kHz, 5.43 ?W, 40 nm, 128 kb, symmetrical 10T subthreshold SRAM with tri-state bit-line. Microelectronics Journal, 51, 89-98.

[22]. Zamani, M., Hassanzadeh, S., Hajsadeghi, K., & Saeidi, R. (2013). A 32 kb 90 nm 9T-cell sub-threshold SRAM with improved read and write SNM. In Design & Technology th of Integrated Systems in Nanoscale Era (DTIS), 2013 8 International Conference on (pp. 104-107). IEEE.

i-manager's Journal on Circuits and Systems (JCIR)

Current Issue Vol. 11 Issue 2

Most Read

Most Cited

Volume 6 Issue 1 December - February 2018

Loss Distribution Methodology with a Sense Of Emission Dispatch

Srilatha Dande* , Sivanagaraju Sirigiri**

* Research Scholar, JNT University, Kakinada, Andhra Pradesh, India. ** Professor, Department of Electrical and Electronics Engineering, University College of Engineering, JNT University, Kakinada, Andhra Pradesh, India

Dande, S., and Sirigiri, S. (2018). Loss Distribution Methodology With A Sense Of Emission Dispatch. i-manager’s Journal on Circuits and Systems, 6(1), 1-9. https://doi.org/10.26634/jcir.6.1.14037

Abstract

References

Full Article (HTML)

Pdf

VLSI Design of High Performance DA-Based Reconfigurable FIR Digital Filter For ASIC and FPGA Implementation

P. Lokesh* , S.Chandana **, U.Somalatha ***

*-*** Assistant Professor, Department of Electronics and Communication Engineering, VEMU Institute of Technology, P. Kothakota, India.

Lokesh, P., Chandana, S., and Somalatha, U. (2018). VLSI Design Of High Performance DA-Based Reconfigurable FIR Digital Filter For ASIC and FPGA Implementation. i-manager’s Journal on Circuits and Systems, 6(1), 8-13. https://doi.org/10.26634/jcir.6.1.14494

Abstract

References

Full Article (HTML)

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FPGA Implementation of Reversible High-Speed Carry Skip Adder and Carry Skip BCD Adder

K. Rajesh * , G. Umamaheswara Reddy**

* Research Scholar, Department of Electronics and Communication Engineering, Sri Venkateswara University, Tirupati, Andhra Pradesh, India. ** Professor, Department of Electronics and Communication Engineering, Sri Venkateswara University, Tirupati, Andhra Pradesh, India.

Rajesh, K., and Reddy, G. U. (2018). FPGA Implementation of Reversible High-Speed Carry Skip Adder and Carry Skip BCD Adder. i-manager’s Journal on Circuits and Systems, 6(1), 14-19. https://doi.org/10.26634/jcir.6.1.14496

Abstract

References

Full Article (HTML)

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Low Power Optimization Technique Based Linear Feedback Shift Register

Dharmendra Singh* , Ankit Singh**, Prachi Agrawal***, Harshita Agrawal****

*-** Assistant Professor, Department of Electronics and Telecommunication Engineering, SSIPMT, Raipur, India. ***-**** UG Scholar, Department of Electronics and Telecommunication Engineering, SSIPMT, Raipur, India.

Singh, D., Singh, A., Agrawal, P., and Agrawal, H. (2018). Low Power Optimization Technique Based Linear Feedback Shift Register. i-manager’s Journal on Circuits and Systems, 6(1), 20-24. https://doi.org/10.26634/jcir.6.1.14058

Abstract

References

Full Article (HTML)

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Performance Parameters of Low Power SRAM cells: A Review

Nidhi Tiwari* , Vaibhav Neema**, Kamal J Rangra***, Yogesh Chandra Sharma****

Tiwari, N., Neema, V., Rangra, K. J., and Sharma, Y. C. (2018). Performance Parameters of Low Power SRAM cells: A Review. i-manager’s Journal on Circuits and Systems, 6(1), 25-34. https://doi.org/10.26634/jcir.6.1.14495

Abstract

References

Full Article (HTML)

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* Research Scholar, JNT University, Kakinada, Andhra Pradesh, India.

** Professor, Department of Electrical and Electronics Engineering, University College of Engineering, JNT University, Kakinada, Andhra Pradesh, India

P. Lokesh* , S.Chandana , U.Somalatha *

* Research Scholar, Department of Electronics and Communication Engineering, Sri Venkateswara University, Tirupati, Andhra Pradesh, India.

** Professor, Department of Electronics and Communication Engineering, Sri Venkateswara University, Tirupati, Andhra Pradesh, India.

Dharmendra Singh* , Ankit Singh, Prachi Agrawal*, Harshita Agrawal****

- Assistant Professor, Department of Electronics and Telecommunication Engineering, SSIPMT, Raipur, India.

-**** UG Scholar, Department of Electronics and Telecommunication Engineering, SSIPMT, Raipur, India.

Nidhi Tiwari* , Vaibhav Neema, Kamal J Rangra*, Yogesh Chandra Sharma****