i-manager Publications

i-manager's Journal on Circuits and Systems (JCIR)

Current Issue Vol. 11 Issue 2

Voltage Stability and Power Loss Minimization with UPFC using Heuristic and Hybrid Heuristic Methods
Design and Analysis of Voltage Difference Transconductance Amplifier (VDTA) at FINFET CMOS Technology
Efficient Logic Cell Design for Ultralow-Energy Subthreshold Operation in Wearable Biomedical Systems
Design and Optimization of MSI-Enabled Multi-Precision Binary Multiplier Architecture
Analysis of Carbon Nanotube for Low Power Nano Electronics Applications

Most Cited

Volume 4 Issue 2 March - May 2016

Research Paper

Distribution Systems Reliability Analysis with Power Quality issues and Neutral Currents Compensation Mistreatment MLI-DSTATCOM

T. Rakesh* , V. Madhusudhan, M. Sushama*

* Research Scholar, Department of Electrical and Electronics Engineering, Jawaharlal Nehru Technical University, Hyderabad, India.

Principal & Dean, Kandula Obul Reddy Memorial College of Engineering, Kadapa, India.

Professor, Department of Electrical and Electronics Engineering, Jawaharlal Nehru Technical University, Hyderabad, India.

Rakesh, T., Madhusudhan, V., and Sushama, M. (2016). Distribution Systems Reliability Analysis with Power Quality issues and Neutral Currents Compensation Mistreatment MLI-DSTATCOM. i-manager’s Journal on Circuits and Systems, 4(2), 1-16. https://doi.org/10.26634/jcir.4.2.8097

Abstract

The “Multilevel Converter” has a massive interest at intervals for the vigour programs enterprise. The fundamental constitution of the construction converter is to decompose a curving voltage from some stages of voltages. Construction voltage offer converters area unit manufacturing as a latest breed of energy converter choice for prime energy applications. These converter topologies will generate high-quality voltage waveforms with vigor semiconductor switches acting at a frequency shut. Among the three construction converter topologies, the five-level and 7-level construction convertors constitute a promising replacement, providing a standard style that will be extended to permit an electrical device-less affiliation. This paper offers a three-segment, five stages and 7 stages cascaded construction voltage supply electrical converter headquartered DSTATCOM for vigour line learning to create stronger vigour satisfactory at intervals of the distribution network. Eventually, a curving PWM (SPWM) procedure is adopted to look at the potency of MLI based DSTATCOM. The outcomes the area unit brought by suggests that of Mat science lab / Simulink application package deal.

References

[1]. Bhim Singh, Kamal Al-Haddad and Ambrish Chandra, (1999). “A New Control Approach to 3-phase Active Filter for Harmonics and Reactive Power Compensation”. IEEE Trans. on Power Systems, Vol. 46, No. 5, pp.133-138.

[2]. W. K. Chang, W. M. Grady, Austin, and M. J. Samotyj, (1994). “Meeting IEEE-519 Harmonic Voltage and Voltage Distortion Constraints with an Active Power Line Conditioner”. IEEE Trans on Power Delivery, Vol. 9, No. 3, pp. 1531-1537.

[3]. Hirofumi Akagi, (1994). “Trends in Active Power Line Conditioners”. IEEE Trans on Power Electronics, Vol.9, No.3, pp. 263-268.

[4]. S.K. Meeravali, and K. Chandrasekhar, (2015). “Power Quality Enhancement using Multi-Level Cascaded HBridge Based D-STATCOM with IRP Theory”. International Electrical Engineering Journal (IEEJ), Vol. 6, No. 2, pp. 1756- 1764.

[5]. O. Anaya-Lara, and E. Acha, (2002). “Modeling and Analysis of Custom Power Systems by PSCAD/EMTDC”. IEEE Trans. Power Delivery, Vol. 17, No. 1, pp. 266-272.

[6]. S.V. Ravi Kumar, and S. Sivanagaraju, (2007). “Simualgion of D-Statcom and DVR in Power System”. ARPN Journal of Engineering and Applied Science, Vol. 2, No. 3, pp. 7-13.

[7]. Noramin Ismail, and Wan Norainin Wan Abdullah, (2010). “Enhancement of Power Quality in Distribution th System using D-STATCOM”. The 4 International Power Engineering and Optimization Conference (PEOCO2010), Shah Alam, Selangor, Malaysia. pp. 23-24.

[8]. G. Venkataramana, and B. Johnson, (1997). “A Pulse Width Modulated Power Line Conditioner for Sensitive Load Centers”. IEEE Trans. Power Delivery, Vol. 12, No. 2, pp. 844-849.

[9]. Rosli Omar, Nasrudin Abd Rahim and Mazizan Sulaiman, (2008). “Modeling and Simulation for Voltage Sags/Swells Mitigation using Dynamic Voltage Restorer (DVR)”. Journal of Theoretical and Applied Information Technology, pp. 464-470.

[10]. Bhattacharya Sourabh, (2012). “Applications of DSTATCOM using MATLAB/Simulation in Power System”. Research Journal of Recent Sciences, Vol. 1, pp. 430-433.

[11]. Rodda Shobha Rani, and B. Jyothi, (2011). “VSC Based DSTATCOM & Pulse-Width Modulation for Power Quality Improvement”. International Journal of Engineering Trends and Technology, Vol. 2, No. 2, pp. 38-41.

[12]. M. Mohammadi, and M. Akbari Nasab, (2011). “Voltage Sag Mitigation with D-STATCOM in Distribution Systems”. Australian Journal of Basic and Applied Sciences, Vol. 5, No. 5, pp. 201-207.

[13]. Zhang Bao-hui, Wang Li-yong, Zhang Wen-hao, Zhou De-cai, Yao Feng, Ren Jin-feng, Xie Han, and Yu Gangliang, (2005). “Implementation of Power System Security and Reliability Considering Risk Under Environment of Electricity Market”. IEEE/PES Transmission and Distribution Conference & Exhibition: Asia and Pacific Dalian, China.

[14]. Ignacio Hernando-Gil,Irinel-Sorin Ilie, and Sasa Z. Djokic, (2016). “Reliability Planning of Active Distribution Systems Incorporating Regulator Requirements and Network-reliability Equivalents”. IET Gener. Transm. Distrib., Vol. 10, No. 1, pp. 93-106.

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Research Paper

An Optimized Low Power Self-Resetting Logic Design Approach

Shivani Kulshrestha* , Vikas Kumar Rai**

* PG Scholar, Department of Electronics and Communication Engineering, SIT, Mathura, U.P., India.

** Associate Professor, Department of Electronics and Communication Engineering, SIT, Mathura, U.P., India.

Kulshrestha, S., and Rai, V.K. (2016). An Optimized Low Power Self-Resetting Logic Design Approach. i-manager’s Journal on Circuits and Systems, 4(2), 17-21. https://doi.org/10.26634/jcir.4.2.8098

Abstract

This paper presents a new optimized technique to power reduction and performance improvement based on selfresetting logic. The concept of self-resetting logic uses the concept of resetting the output logic automatically after a certain time span. The proposed circuit eliminates the problems of SRLGDI logic proposed previously. SRLGDI was proven to be better than dynamic logic, CMOS self-resetting logic and GDI. Three designs of full adders were made using SRLGDI and a final proposed design was made using modified SRLGDI logic and compared to three SRLGDI designs to prove the performance improvement achieved using the modified SRLGDI logic.

References

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[10]. K. K. Kavehei, O. Rouholamini, M. Sahafi, A. Mehrabi, S., and Dadkhahi, N., (2008). “Low-Power and High- Performance 1-Bit CMOS Full-Adder Cell”. J. Comput., Vol. 3, No. 2, pp. 48–54.

[11]. Parameswar, A., Hara, H., and Sakurai, T., (1994). “A High Speed, Low Power, Swing Restored Pass-Transistor Logic based Multiply and Accumulate Circuit for Multimedia Applications”. In: Proceedings of the IEEE Custom Integrated Circuits Conference, San Diego, CA, Vol. 31, No. 6, pp. 278-281.

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[13]. Srivastava, (1998). “Issues in the Design of Domino th Logic Circuits”. In: Proceedings of the 8 Great Lakes Symposium on VLSI, Lafayette, LA, pp. 108-112.

[14]. Uma, (2011). “4-Bit Fast Adder Design: Topology and Layout with Selfresetting Logic for Low Power VLSI Circuits”. Int. J. Adv. Eng. Sci. Technol., Vol. 7, pp. 197-205.

[15]. Uma R. and Dhavachelvan P. (2012a). “New Low Power Delay Element in Self Resetting Logic with Modified Gated Diffusion Input Technique”. In: IEEE International Conference on Semiconductor Electronics, pp. 507–511.

[16]. Uma R. D, (2012b). “Modified Gate Diffusion Input Technique: A New Technique for Enhancing Performance in Full Adder Circuits”. Procedia Technol., Vol. 6, pp. 74-81.

[17]. Uma R. (2012c). “Low-Power ASIC Adders in Modified Gate Diffusion Input”. In: Proceedings of the Fourth International Conference on Networks & Communications, Chennai, India, Vol. 131, pp. 195-204.

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Research Paper

Analysis of Carbon Nanotube Field-Effect Transistor

Bal Krishnan* , Sanjai Kumar Agarwal, Sanjeev Kumar*

* Assistant Professor, Department of Electronics Engineering, YMCA University of Science and Technology, Faridabad, Haryana, India.

Professor, Department of Electronics Engineering, YMCA University of Science and Technology, Faridabad, Haryana, India.

* Director, DNS College of Engineering and Technology, Amroha, Uttar Pradesh, India.

Krishan, B.,Agarwal, S. K., and Kumar, S. (2016). Analysis of Carbon Nanotube Field-Effect Transistor. i-manager’s Journal on Circuits and Systems, 4(2), 22-29. https://doi.org/10.26634/jcir.4.2.8099

Abstract

This paper explores the insights of the most outstanding application of carbon nanotube in electronic field, the carbon nanotube field-effect transistor (CNFET). The motivation of research in CNFET is fuelled by the unique electrical features of CNT, especially the semiconducting feature. Besides, the continuous effort to find future nanoelectronic device that can perform as excellent as MOSFET also push the research of CNFET to be more aggressive. The first section gives an overview of the structure of CNFET followed by the explanation of CNFET operation as a switching device. The next section provides the comparison between CNFET and MOSFET. In this paper, a comparison is being made between conventional MOSFET and different types of CNFETs, and finally concluded a future replacement of MOSFET. The major difference in CNFETs and MOSFET is that it has CNT in channel instead of Silicon. CNFETs show improved characteristics with scaling of technology. CNFET bandgap is directly affected by its chirality and diameter, which is the biggest advantage over MOSFETs. The study of various types of CNFETs comparison has been made in this paper.

References

[1]. Goldhaber-Gordon, D. et al. (1997). “Overview of Nanoelectronic Devices”. Proceedings of the IEEE, Vol. 85, No. 4, pp. 521-540.

[2]. Neamen, D.A. (2003). Semiconductor Physics and Devices, Third Edition. Avenue of Americas, NY: McGraw-Hill.

[3]. Bohr, M.T. (2002). “Nanotechnology Goals and Challenges for Electronic Applications”. IEEE Transactions on Nanotechnology, Vol. 1, No. 1, pp. 56-62.

[4]. Compano R. et al. (2000). “Technology Roadmap for Nanoelectronics”. Microelectronics Advanced Research Initiative.

[5]. Keshavarzi, A., Roy, K. and Hawkins, C.F. (2000). “Intrinsic Leakage in Deep Submicron CMOS ICs- Measurement Based Test Solutions”. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 8, No. 6, pp.717-723.

[6]. Chen, Z. et al. (2002). “IDDQ Testing for Deep- Submicron ICs: Challenges and Solutions”. IEEE Design and Test of Computers, Vol. 19, No. 2, pp. 24-33.

[7]. Bhushan, Bharat. (2010). Springer Handbook of Nano Technology, Third Edition. Springer.

[8]. Taur, Y. (2002). “CMOS design near the limit of scaling”. IBM J. Ref. & Dev, Vol. 46, No. 2, pp. 213-20.

[9]. Korotkov, A. N. (1997). “Coulomb Blockade and Digital Single Electron Devices”. In Molecular Electronics, pp. 157- 189.

[10]. Hadley, P., Lientschnig, G., and Lai, M. J. (2003). “Single-Electron Transistors”. Institute of Physics Conference Series, Vol. 174, pp. 125-132.

[11]. Goodnick S. M. and Bird, J. (2003). “Quantum Effect and Single Electron Devices”. IEEE Transaction on Nano Technology, Vol. 2, No. 4, pp. 368-383.

[12]. Likharev, K. K. (1999). “Single-Electron Devices and their Applications”. Proceedings of the IEEE, Vol. 87, No. 4, pp. 606-632.

[13]. Casper Lageweg, Cotofana, S. and Vassiliadis, S. (2004). “Single Electron Encoded Latches and Flip Flops”. IEEE Transactions on Nanotechnology, Vol. 3, No. 2, pp. 237-248.

[14]. Takahashi, Y. et al. (2000). “Silicon Single-Electron th Devices and their Applications”. Proceedings of 30 IEEE International Symposium on Multiple-Valued Logic, pp. 411-420.

[15]. Mathews, R. H. (1999). “A New RTD-FET Logic Family”. Proceedings of the IEEE, Vol. 87, No. 4, pp. 596-605.

[16]. Avouris, P. et al. (2003). “Carbon Nanotube Electronics”. Proceedings of the IEEE, Vol. 91, No. 11, pp. 1772-1784.

[17]. Guo, J. and Lundstrom, M.S. (2002). “A Computational Study of Thin-Body, Double-Gate Schottky Barrier MOSFETs”. IEEE Transactions on Electron Devices, Vol. 49, No. 11, pp. 1897-1902.

[18]. Huang, C.K., Zhang, Z.E. and Yang, C.H. (1998). “Two- Dimensional Numerical Simulation of Schottky Barrier MOSFET with Channel Length to 10 nm”. IEEE Transactions on Electron Devices, Vol. 45, No. 4, pp. 842-847.

[19]. Ren, Z. et al. (2000). “The Ballistic Nanotransistors: A Simulation Study”. Proceedings of IEDM.

[20]. Naveh, Y., and Likharev, K.K. (2000). “Modeling of 10- nm-Scale Ballistic MOSFET's”. IEEE Electron Device Letters, Vol. 21, No. 5, pp. 242-244.

[21]. Rahman, A. et al. (2003). “Theory of Ballistic Nano transistors”. IEEE Transactions on Electron Devices, Vol. 50, No. 9, pp. 1853-1864.

[22]. Dresselhaus, M.S. and Avouris, P. (2001). “Introduction to Carbon Materials Research”. Topics Appl. Phys., Vol. 80, pp. 1–9.

[23]. Saito, R., Dresselhaus, G. and Dresselhaus, M.S. (1998). Physical Properties of Carbon Nanotubes. Imperial College London: Imperial College Press.

[24]. Forro, L. and Schoenberger, C (2014). Physical Properties of Multi-wall Nanotubes. Germany: Springer- Verlag Berlin Heidelberg.

[25]. Hoenlein, W. et al. (2004). “Carbon Nanotube Applications in Microelectronics”. IEEE Transactions on Components and Packaging Technologies, Vol. 27, No. 4, pp. 629-634.

[26]. McEuen, P.L., Fuhrer M.S. and Park H. (2002). “Single- Walled Carbon Nanotube Electronics”. IEEE Transactions on Nanotechnology, Vol. 1, No. 1, pp. 78-85.

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[29]. Yao, Z., Dekker, C. and Avouris, P. (2001). “Electrical Transport Through Single-Wall Carbon Nanotubes”. Volume 80 of the series Topics in Applied Physics, pp. 147-171.

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[33]. Martel, R. et al. (2002). “Carbon Nanotube Field Effect th Transistors and Logic Circuits”. Proceedings of the 39 Conference on Design Automation, pp. 94-98.

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[36]. Derycke, V. et al. (2001). “Carbon Nanotube Inter and Intramolecular Logic Gates”. Nano Letters, Vol. 1, No. 9, pp. 453-456.

[37]. Bachtold, A. et al. (2003). “Logic circuits based on carbon nanotubes”. Physica E, Vol. 16, No. 42-46.

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Research Paper

Multimode OTRA Based Semi-Gaussian Shaper

Varun Kumar Ahalawat* , V. Venkatesh Kumar, Cherna Malhotra, Neeta Pandey, Rajeshwari Pandey

- UG Scholar, Department of Electronics and Communication Engineering, Delhi Technological University, Shahbad, Daulatpur, Delhi, India.

-*** Associate Professor, Department of Electronics and Communication Engineering, Delhi Technological University, Shahbad, Daulatpur, Delhi, India.

Ahalawat, V. K., Kumar, V. V., Malhotra,C., Pandey, N., and Pandey, R. (2016). Multimode OTRA Based Semi-Gaussian Shaper. i-manager’s Journal on Circuits and Systems, 4(2), 30-37. https://doi.org/10.26634/jcir.4.2.8100

Abstract

Operational Transresistance Amplifier (OTRA) is a Current Controlled Voltage Source (CCVS) characterized by low impedance, thereby producing circuits insensitive to stray capacitances. This paper presents an OTRA implementation of a multimode semi Gaussian (S-G) shaper that supports voltage and transimpedance modes of operation. A comparative study of performance indicators like Signal to Noise Ratio (SNR) and Total Harmonic Distortion (THD) is included. The results obtained from SPICE simulations using 0.5 μm CMOS technology model parameters depict a perfect Gaussian shaped output waveform that contributes towards decreasing Inter Symbol Interference (ISI) by overcoming irregularities during transmission of pulse in the channel.

References

[1]. Neufeld, N. (2013). “Introduction to Detector Readout and Front End Electronics”. ISOTDQ 2013.

[2]. Geronimo, G. D., and Li, S. (2011). “Shaper Design in CMOS for High Dynamic Range”. IEEE Trans. Nucl. Sci. IEEE Transactions on Nuclear Science, Vol. 58, No. 5, pp. 2382- 2390.

[3]. Knoll, G.F. (1979). Radiation Detection and Measurement. New York: Wiley

[4]. Konrad, M. (1968). “Detector Pulse Shaping for High Resolution Spectroscopy”. IEEE Trans. Nucl. Sci. IEEE Transactions on Nuclear Science, Vol. 15, No. 1, pp. 268-282.

[5]. Salama, K.N., and Soliman, A.M. (1999). “CMOS Operational Transresistance Amplifier for Analog Signal Processing”. Microelectronics Journal, Vol. 30, No. 3, pp. 235-245.

[6]. Pandey, R., Pandey, N., and Paul, S.K. (2012). “MOS-C Third Order Quadrature Oscillator Using OTRA”. 2012 Third I n t e r n a t i o n a l C o n f e re n c e o n C omp u t e r a n d Communication Technology

[7]. Pandey, R., (2014). “Signal processing and generating circuits using OTRA as a building block”. Retrieved from Shodhganga (http://hdl.handle.net/10603/31644), University of Delhi.

[8]. Noulis, T., Deradonis, C., and Siskos, S. (2006). “Design and Comparison of CMOS CCII Based Shapers for Detector nd Readout Front Ends”. IEEE 2 Conf. on Ph.D. Research in Microelectronics and Electronics, pp. 149-152.

[9]. Noulis, T., Deradonis, C., and Siskos, S. (2007a). “Advanced Readout System IC Current Mode Semi- Gaussian Shapers Using CCIIs and OTAs”. VLSI Design, 2007, pp. 1-12.

[10]. Noulis, T., Deradonis, C., and Siskos, S. (2007b). “Design guidelines and comparison of detector readout front end integrated S-G shapers using transconductance circuits”. International Journal of Electronics, Vol. 94, No. 10, pp. 943-959.

[11]. Noulis, T., Deradonis, C., Siskos, S., and Sarrabayrouse, G. (2008). “Particle detector tunable monolithic Semi- Gaussian shaping filter based on transconductance amplifiers”. Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, Vol. 589, No. 2, pp. 330-337.

[12]. Noulis, T., Voulkidou, A., Siskos, S., and Sarrabayrouse, G. (2010). “Current mode low BW-large peaking time CMOS S-G shaper using CA building cells”. Melecon 2010- th 2010 15 IEEE Mediterranean Electrotechnical Conference, pp. 290-295.

[13]. Pandey, N., Pandey, R., and Sayal, A. (2013a). “CDTA based semi Gaussian shapers for detector readout front ends”. 2013 International Conference on Circuits, Power and Computing Technologies (ICCPCT), pp. 703-708.

[14]. Pandey, N., Sayal, A., and Pandey, R. (2013b). “DDCCTA based semi Gaussian shapers for detector readout front ends”. 2013 International Conference on Circuits, Power and Computing Technologies (ICCPCT).

[15]. Mostafa, H., and Soliman, A. M. (2006). “A Modified CMOS Realization of the Operational Transresistance Amplifier (OTRA)”. Frequenz, Vol. 60, No. 3-4.

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Research Paper

OFCC Based Shadow Filter

Prashant Gola* , Prateek Tripathi, Prateek Pahalwan, Neeta Pandey, Rajeshwari Pandey

- UG Scholar, Department of Electronics and Communication Engineering, Delhi Technological University, Shahbad, Daulatpur, Delhi, India.

-*** Associate Professor, Department of Electronics and Communication Engineering, Delhi Technological University, Shahbad, Daulatpur, Delhi, India.

Gola, P., Tripathi, P., Pahalwan, P., Pandey, N., and Pandey, R. (2016). OFCC Based Shadow Filter. i-manager’s Journal on Circuits and Systems, 4(2), 38-44. https://doi.org/10.26634/jcir.4.2.8101

Abstract

This paper proposes an Operational Floating Current Conveyor (OFCC) based shadow filter configuration. The operation of the filter is based on modifying filter performance parameters with the help of gain of active block. This flexibility makes it attractive in comparison to a design, where similar control is achieved by changing values of relatively larger number of components. The proposed filter uses four active blocks (OFCCs), two grounded capacitors, and four grounded resistors and helps achieve low pass controlled low pass, high pass and band pass response. The use of grounded passive components makes proposed configuration, attractive from integrated circuit realization viewpoint. The functionality of the proposed circuit is demonstrated through SPICE simulations using the 0.5 m CMOS process model of MOSIS (AGILENT). The proposed circuit can be readily used in today's multi-standard transceivers in the IF stage for the implementation of frequency agile filters, which offer higher configurability to the transceiver chain and the analog front-end towards various standards of the ever changing industry demands.

References

[1]. Sedra, A.S., and Smith, K.C. (2004). Microelectronic Circuits, Sedra. New York: Oxford University Press.

[2]. Lakys, Y., Fabre, A., and Godarra, B. (2009). “Cognitive and Encrypted Communications, Part 2: 'A New Approach to Active Frequency-Agile Filters and Validation Results for an Agile Bandpass Topology in SiGe-BiCMOS”. Retrieved from http://dx.doi.org/10.1109/ELECO.2009.5355002

[3]. Lakys, Y., and Fabre, A. (2010a). “Shadow filters-new family of second-order filters”. Electron. Lett. Electronics Letters, Vol. 46, No. 4, pp. 276-277.

[4]. Lakys, Y., and A. Fabre, (2010b). “Shadow Filters th Generalisation to N^th -class”. Electron. Lett. Electronics Letters, Vol. 46, No. 14, pp. 985-986.

[5]. Lakys, Y., and Fabre, A. (2011). “A Fully Active Frequency Agile Filter for Multistandard Transceivers”. International Conference on Applied Electronics, pp. 1-7.

[6]. Lakys, Y., and Fabre, A. (2012). “Multistandard transceivers: State-of-the-art and a new versatile implementation for fully active frequency agile filters”. Analog Integrated Circuits and Signal Processing Analog Integr Circ. Sig. Process, Vol. 74, No. 1, pp. 63-78.

[7]. Alaybeyoglu, E., and Kuntman, H. (2015). “A new VDTA based frequency agile filter”. 2015 9^th International Conference on Electrical and Electronics Engineering (ELECO).

[8]. Alaybeyoglu, E., and Kuntman, H. (2016). “A new frequency agile filter structure employing CDTA for positioning”. Retrieved from http://link.springer.com/ article/10.1007/s 10470-016-0770-9?view=classic

[9]. Ghallab, Y., Badawy, W., Kaler, K., El-Ela, M.A., and El- Said, M. (2002a). “A new second-order active universal filter with single input and three outputs using operational floating current conveyor”. The 14^th International Conference on Microelectronics.

[10]. Ghallab, Y., El-Ela, M.A., and Elsaid, M. (2002b). “A novel universal voltage-mode filter with three inputs and single output using only two operational floating current conveyor”. ICM 2000. Proceedings of the 12^th International Conference on Microelectronics.

[11]. Ghallab, Y., and Badawy, W. (2004). “A new differential ph sensor current mode read out circuit using only two operational floating current conveyor”. IEEE International Workshop on Biomedical Circuits and Systems, 2004.

[12]. Ghallab, Y., Badawy, W., Kaler, K., and Maundy, B. (2005). “A Novel Current-Mode Instrumentation Amplifier Based on Operational Floating Current Conveyor”. IEEE Trans. Instrum. Meas. IEEE Transactions on Instrumentation and Measurement, Vol. 54, No. 5, pp. 1941-1949.

[13]. Ghallab, Y.H., Badawy, W., El-Ela, M.A., and El-Said, M.H. (2006). “The operational floating current conveyor and its applications”. Journal of Circuits, Systems and Computers J Circuit Syst Comp, Vol. 15, No. 3, pp. 351-372.

[14]. Ghallab, Y., and Badawy, W. (2006). “A new topology for a current-mode wheatstone bridge”. IEEE Transactions on Circuits and Systems II: Express Briefs IEEE Trans. Circuits Syst. II, Vol. 53, No. 1, pp. 18-22.

[15]. Pandey, N., Nand, D., and Khan, Z. (2013). “Single- Input Four-Output Current Mode Filter Using Operational Floating Current Conveyor”. Active and Passive Electronic Components, pp. 1-8.

[16]. Pandey, N., Nand, D., and Khan, Z. (2014). “Operational Floating Current Conveyor-Based Single-Input Multiple- Output Transadmittance Mode Filter”. Arab J Sci Eng Arabian Journal for Science and Engineering, Vol. 39, No. 11, pp. 7991-8000.

[17]. Pandey, N., Pandey, R., Nand, D., and Kumar, A. (2014a). “Current-mode rectifier configuration based on OFCC”. 2014 International Conference on Signal Propagation and Computer Technology (ICSPCT 2014).

[18]. Pandey, N., Tripathi, P., Pandey, R., and Batra, R. (2014b). “OFCC based logarithmic amplifier”. 2014 International Conference on Signal Processing and Integrated Networks (SPIN).

[19]. Pandey, N., Pandey, R., and Nand, D. (2016a). “Generalised operational floating current conveyor based instrumentation amplifier”. IET Circuits, Devices & Systems, Vol. 10, No. 3, pp. 209-219.

[20]. Pandey, N., Nand, D., Kumar, V.V., Ahalawat, V.K., and Malhotra, C. (2016b). “Realization of OFCC based Transimpedance Mode Instrumentation Amplifier”. IEEE Advances in Electrical and Electronic Engineering, Vol. 14, No. 2.

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