References
[1]. Agrawal Agrawal, (2009). “A New Mixed Gate Diffusion
Input Full Adder Topology for High Speed Low Power Digital
Circuits”. World Appl. Sci. J., Vol. 7, pp. 138-144.
[2]. Aguirrre Agrawal, (2011). “CMOS Full Adders for Energy-
Efficient Arithmetic Applications”. IEEE Trans. Very Large
Scale Integr. VLSI Syst., Vol. 19, No. 4, pp. 718-721.
[3]. Balsara, P.T., and Steiss, D., (1996). “Performance of
CMOS Differential Circuits”. IEEE J. Solid-State Circuits, Vol.
31, No. 6, pp. 841-846.
[4]. Bisdounis, (1998). “A Comparative Study of CMOS
Circuit Design Styles for Low-power High-Speed VLSI
Circuits”. Int. J. Electron. Vol. 84, No. 6, pp. 599-613.
[5]. Chatzigeorgiou, A., and Nikolaidis, S., (2001).
“Modelling the operation of pass transistor and CPL gates”.
Int. J. Electron. Vol. 88, No. 9, pp. 977–1000.
[6]. Ghadiry, M.H, Nadisenejani, M, and Miryahyaei M,
(2010). “A New Full Swing Full Adder Based on a New Logic
Approach”. World Appl. Sci., Vol. 11, No. 7, pp. 808-812.
[7]. Litvin, M.E., and Mourad, S., (2005). “Self-reset logic for
fast arithmetic applications”. IEEE Trans. Very Large Scale
Integr. Syst. Vol. 13, No. 4, pp. 462–475.
[8]. Mirzaee, R.F, Moaiyeri, M.H, and Navi, K., (2010). “High
Speed NPCMOS and Multi-output Dynamic Full Adder
Cells”. World Acad. Sci. Eng. Technol., Vol. 39, pp. 698-704.
[9]. Morgenshtein, A., Fish A., and Wagner, I.A, (2002).
“Gate-Diffusion Input (GDI): A Power-Efficient Method for
Digital Combinatorial Circuits”. IEEE Trans. VLSI, Vol. 10, No. 5, pp. 566-581.
[10]. K. K. Kavehei, O. Rouholamini, M. Sahafi, A. Mehrabi,
S., and Dadkhahi, N., (2008). “Low-Power and High-
Performance 1-Bit CMOS Full-Adder Cell”. J. Comput., Vol.
3, No. 2, pp. 48–54.
[11]. Parameswar, A., Hara, H., and Sakurai, T., (1994). “A
High Speed, Low Power, Swing Restored Pass-Transistor Logic
based Multiply and Accumulate Circuit for Multimedia
Applications”. In: Proceedings of the IEEE Custom
Integrated Circuits Conference, San Diego, CA, Vol. 31,
No. 6, pp. 278-281.
[12]. Shubin, (2011). “New CMOS Circuit Implementation of
a One Bit Full Adder Cell”. Russ. Microlectron. Vol. 40, No. 2,
pp. 119-127.
[13]. Srivastava, (1998). “Issues in the Design of Domino
th Logic Circuits”. In: Proceedings of the 8 Great Lakes
Symposium on VLSI, Lafayette, LA, pp. 108-112.
[14]. Uma, (2011). “4-Bit Fast Adder Design: Topology and
Layout with Selfresetting Logic for Low Power VLSI Circuits”.
Int. J. Adv. Eng. Sci. Technol., Vol. 7, pp. 197-205.
[15]. Uma R. and Dhavachelvan P. (2012a). “New Low
Power Delay Element in Self Resetting Logic with Modified
Gated Diffusion Input Technique”. In: IEEE International
Conference on Semiconductor Electronics, pp. 507–511.
[16]. Uma R. D, (2012b). “Modified Gate Diffusion Input
Technique: A New Technique for Enhancing Performance
in Full Adder Circuits”. Procedia Technol., Vol. 6, pp. 74-81.
[17]. Uma R. (2012c). “Low-Power ASIC Adders in Modified
Gate Diffusion Input”. In: Proceedings of the Fourth
International Conference on Networks & Communications,
Chennai, India, Vol. 131, pp. 195-204.