Voltage Stability and Power Loss Minimization with UPFC using Heuristic and Hybrid Heuristic Methods
Design and Analysis of Voltage Difference Transconductance Amplifier (VDTA) at FINFET CMOS Technology
Efficient Logic Cell Design for Ultralow-Energy Subthreshold Operation in Wearable Biomedical Systems
Design and Optimization of MSI-Enabled Multi-Precision Binary Multiplier Architecture
Analysis of Carbon Nanotube for Low Power Nano Electronics Applications
Loss Distribution Methodology with a Sense Of Emission Dispatch
Low Power Optimization Technique Based Linear Feedback Shift Register
Leakage Power Reduction Using Multi Modal Driven Hierarchical Power Mode Switches
Performance of Continuous and Discontinuous Space Vector Pwm Technique for Open End Winding Induction Motor Drive
Validation of IOV chain using OVM Technique
Electronic Circuit Design for Electromagnetic Compliance through Problem-Based Learning
Trioinformatics: The Innovative and Novel Logic Notation That Defines, Explains, and Expresses the Rational Application of The Law of Trichotomy for Digital Instrumentation and Circuit Design
Design Of a Novel Gated 5T SRAM Cell with Low Power Dissipation in Active and Sleep Mode
A Two Stage Power Optimized Implantable Neural Amplifier Based on Cascoded Structures
An Efficient Hybrid PFSCL based Implementation of Asynchronous Pipeline
A robust method for stabilizing Fully Differential (FD) two stage amplifiers is presented in Figure 2(c) which is fast, guaranteed latch free, low offset while offering simpler tracking of compensation with some increase in power dissipation. Submicron processes with supply voltages ranging from 0.7 to 1.2 V place an ever increasing demand for efficient use of analog supply budget headroom, Common Mode (CM) offset (VOSCM ), differential offset (Vos), and noise erode dynamic range. Common Mode (CM) offset is an often overlooked error contribution of the CM feedback amplifier. The desirable qualities of a CM amplifier are, fast settling, latch up free operation under all transient conditions while being low power, contributing low noise, low VADCs to FD circuits, i.e. pipeline (Analog-to-Digital Convertors). It is widely known that, current feedback can be fast, limited only by the current gain bandwidth of the process [1,2]. The proposed CM current amplifier in Figure 2(c) avoids latching states while maintaining Common Mode FeedBack (CMFB) loop stability and simplifying CMFB compensation.
The intensifying trade of transportable electronic devices such as cell phones, laptops, tablet PCs and other handheld devices require minimum power dissipation for retaining the battery life, high reliability and compactness of the system. The highly energy efficient processors and handheld portable systems involve SRAMs as the crucial components which indicate that significant notice has to be given in designing the high performance and power reduced SRAMs. The consumption of power and area penalty of SRAM(Static Random Access Memory) reaches a higher value accordingly with the scaling down of technology. This Paper mainly deals with the subthreshold leakage current which is the predominant leakage component of SRAM cell and circuit level leakage reduction techniques to obtain subthreshold leakage reduced SRAM cell. Various SRAM cell topologies are summarized in the point of subthreshold leakage reduction and their subthreshold and gate leakage currents Hold SNM at various temperatures and process the corners which have been measured and compared. Simulations are performed with 90nm CMOS technology process file using Mentor Graphics. Finally, the 8T SRAM bitcell has been identified as the best cell topology designed with dynamic V DD scaling technique, which reports considerable leakage reduction over 6T at all process corners. Simulation results revealed that there is a considerable improvement of hold SNM at 25ºC in 8T over other SRAM cell topologies.
The paper introduces a Real Time monitoring Automatic analysis and Neutralization of HNO3 in Acid Storage and Treatment Plant (ASTP). This system aims to reduce the variability and processing time involved in manual neutralization while maintaining comparable results. The used acids like HNO , HF are acidic that causes environment hazards so it 3 should be treated properly. The conventional method employs sampling the acid for pH measure and then manually neutralizes it. This system proposes pH monitoring at running condition and neutralizing with lime automatically so as to maintain pH level at 6.5 to 8.0. and also the whole plant with various parameters like lime milk level, pressure, temperature, flow of acid will be monitored integrally and automatically by the implementation of PLC.
Autistic children lack communication and socialization showing stereotyped behavior. This paper is emphasizing on a hardware and a software to identify the needs of such children and also to provide speech therapy. Software has been designed to engage the child throughout the day and helps the parents to identify their needs. In the hardware technique vocal status is tracked from the neck by measuring the glottal airflow estimates. Clinically the treatment can be enhanced by making the child to speak continuously via a biofeedback.
Power reduction is a main parameter to design VLSI circuits. In this paper, to design a number of D-flip flop performing at the same time, the given clock signal is reduced using multi bit flip-flop. The multi bit flip flop is mainly used to improve the clock power for the given common clock signal and to reduce the switching power. This method is performed to replace some D flip-flop into multi bit flip-flops with the given common clock input. In this proposed technique, first step is to identify the flip flops and its placed location, second step is to build the combination table mainly by merging the flip flop and removing the unwanted merging flip-flops, final step is to assign the region , place the flip flop in these flip-flops merging and replacing the merging location. By using this method, the result is used to reduce the power to 24mW and area by reducing to 35 gate count ,because this method considers the area measured as the number of gate count in the merging flip flop.
